Specifications
Table Of Contents
- Contents
- Tables
- Figures
- 1 Introduction
- 2 Interface Characteristics
- 2.1 Application Interface
- 2.1.1 Pad Assignment
- 2.1.2 Signal Properties
- 2.1.3 USB Interface
- 2.1.4 Serial Interface ASC0
- 2.1.5 Serial Interface ASC1
- 2.1.6 Inter-Integrated Circuit Interface
- 2.1.7 UICC/SIM/USIM Interface
- 2.1.8 Enhanced ESD Protection for SIM Interfaces
- 2.1.9 Digital Audio Interface
- 2.1.10 Analog-to-Digital Converter (ADC)
- 2.1.11 RTC Backup
- 2.1.12 GPIO Interface
- 2.1.13 Control Signals
- 2.1.14 JTAG Interface
- 2.1.15 eMMC Interface
- 2.2 GSM/UMTS/LTE Antenna Interface
- 2.3 GNSS Antenna Interface
- 2.4 Sample Application
- 2.1 Application Interface
- 3 GNSS Interface
- 4 Operating Characteristics
- 5 Mechanical Dimensions and Mounting
- 6 Regulatory and Type Approval Information
- 7 Document Information
- 8 Appendix
Cinterion
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ALAS5V Hardware Interface Description
4.2 Power Up/Power Down Scenarios
96
ALAS5V_HID_v00.030a 2019-03-20
Confidential / Preliminary
Page 70 of 124
4.2.2 Signal States after First Startup
Table 22 describes the various states each interface signal passes through after startup and
during operation.
Signals are in an initial state while the module is initializing. Once the startup initialization has
completed, i.e. when the software is running, all signals are in defined state. The state of sev-
eral signals will change again once the respective interface is activated or configured by AT
command.
Table 22: Signal states
Signal name Pad no. Reset phase
(ignition)
0 - 100ms
Hardware init
100ms - 5s
Firmware init
5s - 32s
System active
>32s
CCIN1 N19 PD PU PU PU
CCRST1 L19 L L 1.8V/3V Data L
CCIO1 J19 L L 1.8V/3V Data L
CCCLK1 M19 PD PD PD --> 1.8V/3V CLK
--> L
L
CCIN2 N18 Tri PD --> PU PU --> Tri Tri
CCRST2 K18 Tri PD PD --> L L
CCIO2 J18 Tri PD PD --> L L
CCCLK2 M18 Tri PD PD --> L L
RXD0 F18 Tri PD --> PU PU --> Tri Tri
TXD0 H19 Tri PD --> PU PU --> Tri Tri
CTS0 G19 Tri PD --> PU PU --> Tri Tri
RTS0 G20 Tri PD --> PU PU --> Tri Tri
DSR0 F17 PD PD PD PD
DTR0 F19 Tri PD PD PD
DCD0 G18 PD PD --> PU -->
PD
PD PD
RING0 J20 Tri PD --> PU PU PU
RXD1 R9 Tri PD --> PU PU --> Tri Tri
TXD1 R8 Tri PD --> PU PU --> Tri Tri
CTS1 R7 Tri PD --> PU PU --> Tri Tri
RTS1 R6 Tri PD --> PU PU --> Tri Tri
DIN2 N9 Tri PU --> PD PD PD
BCLK2 N10 Tri PD PD PD
FSC2 N7 Tri PD PD PD
MCLK P11 Tri PD PD PD
DOUT2 N8 Tri PD PD PD
I2CDAT1 M9 Tri PD --> PU PU PU
I2CCLK1 M10 Tri PD --> PU PU PU
EMERG_OFF F16 PD/PU PU PU PU
PCIE_HOST_
RST
R11 Tri PD --> L L L
PCIE_HOST_
WAKE
R10 Tri PD PD --> Tri Tri
PCIE_CLK_ REQ R14 Tri PD PD --> L L
PCIE_CLK_P P16 Tri/PCIe Tri/PCIe 2 packets activity
(11s and 13s)
Tri/PCIe