Specifications

Table Of Contents
Cinterion
®
ALAS5V Hardware Interface Description
Figures
124
ALAS5V_HID_v00.030a 2019-03-20
Confidential / Preliminary
Page 7 of 124
Figures
Figure 1: ALAS5V system overview.............................................................................. 15
Figure 2: ALAS5V block diagram.................................................................................. 16
Figure 3: ALAS5V bottom view: Pad assignments........................................................ 19
Figure 4: ALAS5V top view: Pad assignments.............................................................. 20
Figure 5: USB circuit ..................................................................................................... 30
Figure 6: Serial interface ASC0..................................................................................... 31
Figure 7: Serial interface ASC1..................................................................................... 32
Figure 8: I
2
C interface connected to VEXT ................................................................... 33
Figure 9: First UICC/SIM/USIM interface ...................................................................... 35
Figure 10: Second UICC/SIM/USIM interface................................................................. 35
Figure 11: SIM interfaces - enhanced ESD protection.................................................... 36
Figure 12: PCM timing short frame (master, 4096KHz, 16kHz sample rate) .................. 37
Figure 13: I
2
S timing (master mode) ............................................................................... 38
Figure 14: PWR_IND signal ............................................................................................ 40
Figure 15: eMMC power supply ...................................................................................... 42
Figure 16: Antenna pads (top view) ................................................................................ 49
Figure 17: Embedded Stripline line arrangement............................................................ 50
Figure 18: Micro-Stripline line arrangement samples...................................................... 51
Figure 19: Routing to application‘s RF connector ........................................................... 52
Figure 20: Resistor measurement used for antenna detection ....................................... 53
Figure 21: Basic circuit for antenna detection................................................................. 54
Figure 22: Supply voltage for active GNSS antenna....................................................... 56
Figure 23: ESD protection for passive GNSS antenna ................................................... 57
Figure 24: ALAS5V sample application........................................................................... 59
Figure 25: Sample level conversion circuits.................................................................... 61
Figure 26: Antenna detection circuit sample - Overview................................................. 62
Figure 27: Antenna detection circuit sample - Schematic ............................................... 63
Figure 28: Power-on with IGT ......................................................................................... 69
Figure 29: Signal states during turn-off procedure.......................................................... 74
Figure 30: Timing of IGT if used as ON/OFF switch ....................................................... 75
Figure 31: Shutdown by EMERG_OFF signal................................................................. 76
Figure 32: Restart by EMERG_OFF signal..................................................................... 76
Figure 33: Overall shutdown sequence........................................................................... 77
Figure 34: Power saving and paging in GSM networks .................................................. 83
Figure 35: Power saving and paging in WCDMA networks............................................. 84
Figure 36: Power saving and paging in LTE networks.................................................... 85
Figure 37: Decoupling capacitor(s) for BATT+................................................................ 86
Figure 38: Power supply limits during transmit burst....................................................... 94
Figure 39: Board and ambient temperature differences.................................................. 95
Figure 40: ALAS5V – top and bottom view ..................................................................... 97
Figure 41: Dimensions of ALAS5V (all dimensions in mm)............................................. 98
Figure 42: Land pattern (top layer).................................................................................. 99
Figure 43: Recommended design for 110 micron thick stencil (top layer) .................... 100
Figure 44: Reflow Profile............................................................................................... 101
Figure 45: Shipping tray dimensions............................................................................. 105
Figure 46: Moisture Sensitivity Label ............................................................................ 106
Figure 47: Humidity Indicator Card - HIC ...................................................................... 107
Figure 48: Reference equipment for type approval....................................................... 112