Specifications
Table Of Contents
- Contents
- Tables
- Figures
- 1 Introduction
- 2 Interface Characteristics
- 2.1 Application Interface
- 2.1.1 Pad Assignment
- 2.1.2 Signal Properties
- 2.1.3 USB Interface
- 2.1.4 Serial Interface ASC0
- 2.1.5 Serial Interface ASC1
- 2.1.6 Inter-Integrated Circuit Interface
- 2.1.7 UICC/SIM/USIM Interface
- 2.1.8 Enhanced ESD Protection for SIM Interfaces
- 2.1.9 Digital Audio Interface
- 2.1.10 Analog-to-Digital Converter (ADC)
- 2.1.11 RTC Backup
- 2.1.12 GPIO Interface
- 2.1.13 Control Signals
- 2.1.14 JTAG Interface
- 2.1.15 eMMC Interface
- 2.2 GSM/UMTS/LTE Antenna Interface
- 2.3 GNSS Antenna Interface
- 2.4 Sample Application
- 2.1 Application Interface
- 3 GNSS Interface
- 4 Operating Characteristics
- 5 Mechanical Dimensions and Mounting
- 6 Regulatory and Type Approval Information
- 7 Document Information
- 8 Appendix
Cinterion
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ALAS5V Hardware Interface Description
2.4 Sample Application
67
ALAS5V_HID_v00.030a 2019-03-20
Confidential / Preliminary
Page 60 of 124
2.4.1 Prevent Back Powering
Because of the very low power consumption design, current flowing from any other source into
the module circuit must be avoided in any case, for example reverse current from high state
external control lines while the module is powered down. Therefore, the external application
must be designed to prevent reverse current flow. Otherwise there is the risk of undefined
states of the module during startup and shutdown or even of damaging the module. A simple
solution preventing back powering is the usage of VEXT for level shifters, as Figure 25 shows.
If level shifters are not really required, it is also possible to employ buffers.
While the module is in power down mode, VEXT must have a level lower than 0.3V after a cer-
tain time. If this is not the case the module is fed back by the application interface - recognizing
such a fault state is possible by VEXT.