Specifications
Table Of Contents
- Contents
- Tables
- Figures
- 1 Introduction
- 2 Interface Characteristics
- 2.1 Application Interface
- 2.1.1 Pad Assignment
- 2.1.2 Signal Properties
- 2.1.3 USB Interface
- 2.1.4 Serial Interface ASC0
- 2.1.5 Serial Interface ASC1
- 2.1.6 Inter-Integrated Circuit Interface
- 2.1.7 UICC/SIM/USIM Interface
- 2.1.8 Enhanced ESD Protection for SIM Interfaces
- 2.1.9 Digital Audio Interface
- 2.1.10 Analog-to-Digital Converter (ADC)
- 2.1.11 RTC Backup
- 2.1.12 GPIO Interface
- 2.1.13 Control Signals
- 2.1.14 JTAG Interface
- 2.1.15 eMMC Interface
- 2.2 GSM/UMTS/LTE Antenna Interface
- 2.3 GNSS Antenna Interface
- 2.4 Sample Application
- 2.1 Application Interface
- 3 GNSS Interface
- 4 Operating Characteristics
- 5 Mechanical Dimensions and Mounting
- 6 Regulatory and Type Approval Information
- 7 Document Information
- 8 Appendix
Cinterion
®
ALAS5V Hardware Interface Description
2.1 Application Interface
67
ALAS5V_HID_v00.030a 2019-03-20
Confidential / Preliminary
Page 38 of 124
2.1.9.2 Inter-IC Sound Interface
The Inter-IC Sound Interface is a standardized bidirectional I
2
S based digital audio interface for
transmission of mono voice signals for telephony services.
An activation of the I
2
S line is possible only out of call and out of tone presentation. The I
2
S
properties and capabilities comply with the requirements layed out in the Phillips I2S Bus Spec-
ifications, revised June 5, 1996.
The I
2
S interface has the following characteristics:
• Bit clock mode: Master, optional master clock output
• Sampling rate: 8KHz (narrowband), 16KHz (wideband)
• 256kHz bit clock at 8kHz sample rate
• 512kHz bit clock at 16kHz sample rate
• Frame length: 32 bit stereo voice signal (16 bit word length)
• Optional Master clock: 2048KHz (8KHz sample rate) or 4096KHz (16KHz sample rate)
Table 9 lists the available I
2
S interface signals, Figure 13 shows the I
2
S timing.
Figure 13: I
2
S timing (master mode)
Table 9: Overview of I
2
S pin functions
Signal name on
SMT application
interface
Signal
configuration
inactive
Signal
direction:
Master
Description
DOUT2 PD O I
2
S data from ALAS5V to external codec
DIN2 PD I I
2
S data from external codec to ALAS5V
FSC2 PD O Frame synchronization signal to/from external
codec Word alignment (WS)
BCLK2 PD O Bit clock to external codec. Note: If the BCLK2 sig-
nal is permanently provided (AT^SAIC parameter
<clk_mode> = 0), the module will no longer enter its
power save (SLEEP) state.
MCLK PD O I
2
S Master to supply external codecs without PLL.
BCLK2
DOUT2
DIN2
FSC2
MSB
MSB
LSB
LSB
14 13
14 13
1
1
12
12
2
2
MSB
MSB
125 µs