Specifications
Table Of Contents
- Contents
- Tables
- Figures
- 1 Introduction
- 2 Interface Characteristics
- 2.1 Application Interface
- 2.1.1 Pad Assignment
- 2.1.2 Signal Properties
- 2.1.3 USB Interface
- 2.1.4 Serial Interface ASC0
- 2.1.5 Serial Interface ASC1
- 2.1.6 Inter-Integrated Circuit Interface
- 2.1.7 UICC/SIM/USIM Interface
- 2.1.8 Enhanced ESD Protection for SIM Interfaces
- 2.1.9 Digital Audio Interface
- 2.1.10 Analog-to-Digital Converter (ADC)
- 2.1.11 RTC Backup
- 2.1.12 GPIO Interface
- 2.1.13 Control Signals
- 2.1.14 JTAG Interface
- 2.1.15 eMMC Interface
- 2.2 GSM/UMTS/LTE Antenna Interface
- 2.3 GNSS Antenna Interface
- 2.4 Sample Application
- 2.1 Application Interface
- 3 GNSS Interface
- 4 Operating Characteristics
- 5 Mechanical Dimensions and Mounting
- 6 Regulatory and Type Approval Information
- 7 Document Information
- 8 Appendix
Cinterion
®
ALAS5V Hardware Interface Description
2.1 Application Interface
67
ALAS5V_HID_v00.030a 2019-03-20
Confidential / Preliminary
Page 37 of 124
2.1.9 Digital Audio Interface
ALAS5V has two digital audio interfaces (DAIs) that can be employed as inter pulse code mod-
ulation (PCM) or Inter-IC Sound (I
2
S) interface. Default setting is pulse code modulation.
Please note that the first DAI is reserved for future use.
2.1.9.1 Pulse Code Modulation Interface (PCM)
ALAS5V's PCM interface can be used to connect audio devices capable of pulse code modu-
lation. The PCM functionality is limited to the use of wideband codecs with 16kHz sample rate
only. The PCM interface runs at 16 kHz sample rate (62.5µs frame length), while the signal pro-
cessing maintains this rate in a wideband AMR call or samples automatically down to 8kHz in
a narrowband call. Therefore, the PCM sample rate is independent of the audio bandwidth of
the call.
The PCM interface has the following implementation:
• Master mode
• Short frame synchronization
• 16kHz/8kHz sample rate
• 4096/1024/512/256 kHz bit clock at 16kHz sample rate
• 2048/512/256/128 kHz bit clock at 8kHz sample rate
Table 8 lists the available PCM interface signals.
Note: PCM data is always formatted as 16-bit uncompressed two’s complement. Also, all PCM
data and frame synchronization signals are written to the PCM bus on the rising clock edge and
read on the falling edge.
The timing of a PCM short frame is shown in Figure 12.
Figure 12: PCM timing short frame (master, 4096KHz, 16kHz sample rate)
Table 8: Overview of PCM pin functions
Signal name Signal
direction:
Master
Description
DOUT2 O PCM Data from ALAS5V to external codec
DIN2 I PCM Data from external codec to ALAS5V
FSC2 O Frame synchronization signal to external codec
BCLK2 O Bit clock to external codec. Note: If the BCLK2 signal is permanently
provided (AT^SAIC parameter <clk_mode> = 0), the module will no
longer enter its power save (SLEEP) state.
MSB
MSB
LSB
LSB
14 13
14 13
1
1
12
12
2
2
MSB
MSB
62.5 µs
BCLK2
FSC2
DOUT2
DIN2