Specifications
Table Of Contents
- Contents
- Tables
- Figures
- 1 Introduction
- 2 Interface Characteristics
- 2.1 Application Interface
- 2.1.1 Pad Assignment
- 2.1.2 Signal Properties
- 2.1.3 USB Interface
- 2.1.4 Serial Interface ASC0
- 2.1.5 Serial Interface ASC1
- 2.1.6 Inter-Integrated Circuit Interface
- 2.1.7 UICC/SIM/USIM Interface
- 2.1.8 Enhanced ESD Protection for SIM Interfaces
- 2.1.9 Digital Audio Interface
- 2.1.10 Analog-to-Digital Converter (ADC)
- 2.1.11 RTC Backup
- 2.1.12 GPIO Interface
- 2.1.13 Control Signals
- 2.1.14 JTAG Interface
- 2.1.15 eMMC Interface
- 2.2 GSM/UMTS/LTE Antenna Interface
- 2.3 GNSS Antenna Interface
- 2.4 Sample Application
- 2.1 Application Interface
- 3 GNSS Interface
- 4 Operating Characteristics
- 5 Mechanical Dimensions and Mounting
- 6 Regulatory and Type Approval Information
- 7 Document Information
- 8 Appendix
Cinterion
®
ALAS5V Hardware Interface Description
1.4 Circuit Concept
16
ALAS5V_HID_v00.030a 2019-03-20
Confidential / Preliminary
Page 16 of 124
1.4 Circuit Concept
Figure 2 shows a block diagram of the ALAS5V module and illustrates the major functional
components:
Baseband block:
• GSM/UMTS/LTE controller/transceiver/power supply
• NAND/LPDDR2 memory devices
• Application interface (SMT with connecting pads)
RF section:
• RF transceiver
• RF power amplifier/frontend
• RF filter
• GNSS receiver/Front end
• Antenna pad
Figure 2: ALAS5V block diagram
LPDDR2SDRAM
2GBit
NANDFlash
4GBit
38.4MHz
PowerManagement
Basebandcontroller
RFpart
Clocks
LDO
LDO
LDO
LDO
LDO
S1
S2
S3
S4
S5
PMU
LB/MB /HB
PA
GSM
PA
Filter
&
Switches
QLINK RFFE
EBI1
EBI2
GRFC
BATT+
LGAPads
IGT
EMERGOFF
PWR_IND
USB 3.0
USB 2.0
ASC0
ASC1
I2C
2xPCM/I2S
I2S_MCLK
eMMC
2xSIM
GPIO
PCIe
4xADC
ADC
BATT+_RF
GND
ALAS5
ANT_MAIN
ANT_DRX_
MIMO
ANT_GNSS
GNSS_EN
ANT_GNSS_DC