Specifications

25
3706C–MICRO–2/11
AT89LP3240/6440
The MAC operation is performed by executing the MAC AB (A5 A4H) extended instruction. This
two-byte instruction requires nine clock cycles to complete. The operand registers are not modi-
fied by the instruction and the result is stored in the 40-bit M register. MAC AB also updates the
C and OV flags in PSW. C represents the sign of the MAC result and OV is the two’s comple-
ment overflow. Note that MAC AB will not clear OV if it was previously set to one.
Three addition
al extended instructions operate directly on the M register. CLR M (A5 E4H)
clears the entire 40-bit register in two clock cycles. LSL M (A5 23H) and ASR (A5 03H) shift M
one bit to the left and right res pectively. Right shifts are done arithmetically, i.e. the s ign is
preserved.
The 40-bit M register is accessib le 16-bits at a time through a sliding window as shown in Figure
5-5. The MRW
1-0
bits in DSPR (Table 5-1) select which 16-bit segment is currently accessible
through the MACL and MACH addresses. For normal fixed point operations the window can be
fixed to the rank of interest. For example, multiplying two 1.15 format numbers places a 2.30 for-
mat result in the M register. If MRW is set to 10B, a 1.15 value is obtained after performing a
single LSL M.
Figure 5-5. M Register with Sliding Window
As a consequence of the MAC unit, the standard 8x8 MUL AB instruction can support signed
multiplication. The SMLA and SMLB bits in DSPR control the multiplier’s interpretation of the
ACC and B registers, allowing any combination of signed and unsigned operand multiplication.
These bits have no effect on the MAC operation which a
lways multiplies signed-by-signed.
5.2 Enhanced Dual Data Pointers
The AT89LP3240/6440 provides two 16-bit data pointers: DPTR0 formed by the regis ter pair
DPOL and DPOH (82H an 83H), and DPTR1 formed by the register pair DP1L and DP1H (84H
and 85H). The data pointers are used by several instructions to access the program or data
memories. The Data Pointer Configuration Register (DPCF) controls operation of the dual data
pointers (T
able 5-5 on page 28). The DPS bit in DPCF selects which data pointer is currently ref-
erenced by instructions including the DPTR operand. Each data pointer may be accessed at its
respective SFR addresses regardless of the DPS value. The AT89LP3240/6440 provides two
methods for fast context switching of the data pointers:
• Bit 2 of DPCF is hard-wired as a logic 0. The DPS
bit may be toggled (to switch data pointers)
simply by incrementing the DPCF register, without altering other bits in the register
unintentionally. This is the preferred method when only a single data pointer will be used at
one time.
EX: INC DPCF ; Toggle DPS
M 23 – 16 15 – 8 7 – 031 – 2439 – 32
Byte 4 Byte 3 Byte 2 Byte 1 Byte 0
MACH MACL
MACH MACL
MACH MACL
MACH MACL
MRW
1-0
= 00B
MRW
1-0
= 01B
MRW
1-0
= 10B
MRW
1-0
= 11B