Specifications

24
3706C–MICRO–2/11
AT89LP3240/6440
Figure 5-3. Two-cycle ALU Operation (Example: ADD A, #data)
5.1 Multiply–Accumulate Unit (MAC)
The AT89LP3240/6440 includes a multiply and accumulate (MAC) unit that can significantly
speed up many mathematical operations required for digital signal processing. The MAC unit
includes a 16-by-16 bit multiplier and a 40-bit adder that can perform integer or fractiona l multi-
ply-accumulate operation
s on signed 16-bit input values. The MAC unit also includes a 1-bit
arithmetic shifter that will left or right shift the contents of the 40-bit MAC accumulator register
(M).
A block diagram of the MAC unit is shown in Figure 5-4. The 16-bit signed operands are pro-
vided by the register pairs (AX,ACC) and (BX,B) where AX (E1H) and BX (F7H) hold the higher
order bytes. The 16-by-16 bit mu
ltiplication is computed through partial products using the
AT89LP3240/6440’s 8-bit multiplier. The 32-bit signed product is added to the 40-bit M accumu-
lator register. The MAC operation is summarized as follows:
All computation is done in signed two’s complement form.
Figure 5-4. Multiply–Accumulate Unit
System Clock
Tot al Execution Time
Fetch Immediate Operand
T
1
T
2
T
3
ALU Operation Execute
Result Write Back
Fetch Next Instruction
MAC AB: M M AX ACC{, } BX B{,}×+←
M3M4 M2 M1 M0
ACCAX BX B
8 x 8-bit Signed MULT
40-bit ADD
Shifter
MACH MACL
PSW
MRW
SMLA
SMLB