Specifications

23
3706C–MICRO–2/11
AT89LP3240/6440
5. Enhanced CPU
The AT89LP3240/6440 uses an enhanced 8051 CPU that runs at 6 to 12 times the speed of
standard 8051 devices (or 3 to 6 times the speed of X2 8051 devices). The increase in perfor-
mance is due to two factors. First, the CPU fetches one instruction byte from the code memory
every clock cycle. Second, the CPU uses a simple two-stage pipeline to fetch and execu te
instructions in parallel. This basic pipelining concept a
llows the CPU to obtain up to
1MIPS per MHz. A simple example is shown in Figure 5-1.
The 8051 instruction set allows for instructions of variable length from 1 to 3 bytes. In a single-
clock-per-byte-fetch system this means each instruction takes at least as many clocks as it has
bytes to execute. The majority of instr
uctions in the AT89LP3240/6440 follow this rule: the
instruction execution time in clock cycles equals the number of bytes per instruction, with a
few exceptions. Branches and Calls require an additional cycle to compute the target address
and some other complex instructions require multiple cycles. See “Instruction Set Summary” on
page 143. for more detailed information on individua
l instructions. Figures 5-2 and 5-3 show
examples of 1- and 2-byte instructions.
Figure 5-1. Parallel Instruction Fetches and Executions
Figure 5-2. Single-cycle ALU Operation (Example: INC R0)
System Clock
n
th
Instruction
(n+1)
th
Instruction
Fetch Execute
Fetch Execute
Fetch
T
n
T
n+1
T
n+2
(n+2)
th
Instruction
System Clock
Tot al Execution Time
Register Operand Fetch
T
1
T
2
T
3
ALU Operation Execute
Result Write Back
Fetch Next Instruction