Features • 8-bit Microcontroller Compatible with MCS®51 Products • Enhanced 8051 Architecture • • • • • – Single-clock Cycle per Byte Fetch – Up to 20 MIPS Throughput at 20 MHz Clock Frequency – Fully Static Operation: 0 Hz to 20 MHz – On-chip 2-cycle Hardware Multiplier – 16x16 Multiply–Accumulate Unit – 256x8 Internal RAM – 4096x8 Internal Extra RAM – Up to 4KB Extended Stack in Extra RAM – Dual Data Pointers – 4-level Interrupt Priority Nonvolatile Program and Data Memory – 32K/64K Bytes of In-Syst
1. Pin Configurations 1.1 40P6: 40-lead PDIP T2/P1.0 T2EX/P1.1 SDA/P1.2 SCL/P1.3 SS/P1.4 MOSI/P1.5 MISO/P1.6 SCK/P1.7 RST/P4.2 RXD/P3.0 TXD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 WR/P3.6 RD/P3.7 XTAL2/P4.1 XTAL1/P4.0 GND 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDD P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 P4.3 P4.4/ALE P4.5 P2.7/AIN3/A15 P2.6/AIN2/A14 P2.5/AIN1/A13 P2.4/AIN0/A12 P2.3/A11/CCD P2.2/A10/CCC P2.1/A9/CCB P2.
AT89LP3240/6440 44J: 44-lead PLCC 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 7 8 9 10 11 12 13 14 15 16 17 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 P4.3 GND P4.4/ALE P4.5 P2.7/AIN3/A15 P2.6/AIN2/A14 P2.5/AIN1/A13 WR/P3.6 RD/P3.7 XTAL2/P4.1 XTAL1/P4.0 GND GND CCA/A8/AIN0/P2.0 CCB/A9/P2.1 CCC/A10/P2.2 CCD/A11/P2.3 A12/AIN0/P2.4 MOSI/P1.5 MISO/P1.6 SCK/P1.7 RST/P4.2 RXD/P3.0 VDD TXD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 6 5 4 3 2 1 44 43 42 41 40 P1.4/SS P1.3/SCL P1.2/SDA P1.
1.5 Pin Description Table 1-1. AT89LP3240/6440 Pin Description Pin Number TQFP 1 PLCC 7 PDIP 6 VQFN 1 Symbol P1.5 Type I/O I/O I 2 8 7 2 P1.6 I/O I/O I 3 9 8 3 P1.7 I/O I/O I 4 10 9 4 P4.2 I/O I I 5 P3.0 I/O I 6 VDD I 11 7 P3.1 14 12 8 9 15 13 10 16 11 5 11 6 12 7 13 8 10 I/O P1.5: User-configurable I/O Port 1 bit 5. MOSI: SPI master-out/slave-in. When configured as master, this pin is an output. When configured as slave, this pin is an input.
AT89LP3240/6440 Table 1-1. AT89LP3240/6440 Pin Description Pin Number TQFP PLCC PDIP VQFN Symbol Type 17 23 20 17 GND I 18 24 21 18 P2.0 I/O I/O O P2.0: User-configurable I/O Port 2 bit 0. CCA: Timer 2 Channel A Compare Output or Capture Input. A8: External memory interface Address bit 8. 19 25 22 19 P2.1 I/O I/O O P2.1: User-configurable I/O Port 2 bit 1. CCB: Timer 2 Channel B Compare Output or Capture Input. A9: External memory interface Address bit 9. P2.1 I/O I/O O O P2.
Table 1-1. AT89LP3240/6440 Pin Description Pin Number TQFP PLCC PDIP VQFN Symbol Type Description 35 41 37 35 P0.2 I/O O I P0.2: User-configurable I/O Port 0 bit 2. AD2: External memory interface Address/Data bit 2. ADC2: ADC analog input 2. 36 42 38 36 P0.1 I/O O I P0.1: User-configurable I/O Port 0 bit 1. AD1: External memory interface Address/Data bit 1. ADC1: ADC analog input 1. 37 43 39 37 P0.0 I/O O I P0.0: User-configurable I/O Port 0 bit 0.
AT89LP3240/6440 Timer 0 and Timer 1 in the AT89LP3240/6440 are enhanced with two new modes. Mode 0 can be configured as a variable 9- to 16-bit timer/counter and Mode 1 can be configured as a 16-bit auto-reload timer/counter. In addition, the timer/counters may each independently drive an 8-bit precision pulse width modulation output. Timer 2 on the AT89LP3240/6440 serves as a 16-bit time base for a 4-channel Compare/Capture Array with up to four multi-phasic, variable precision (up to 16-bit) PWM outputs.
2.2 System Configuration The AT89LP3240/6440 supports several system configuration options. Nonvolatile options are set through user fuses that must be programmed through the flash programming interface. Volatile options are controlled by software through individual bits of special function registers (SFRs). The AT89LP3240/6440 must be properly configured before correct operation can occur. 2.2.1 Fuse Options Table 2-1 lists the fusable options for the AT89LP3240/6440.
AT89LP3240/6440 2.3 Comparison to Standard 8051 The AT89LP3240/6440 is part of a family of devices with enhanced features that are fully binary compatible with the 8051 instruction set. In addition, most SFR addresses, bit assignments, and pin alternate functions are identical to Atmel's existing standard 8051 products. However, due to the high performance nature of the device, some system behaviors are different from those of Atmel's standard 8051 products such as AT89S52 or AT89C2051.
There is no difference in counting rate between Timer 2’s Auto-Reload/Capture and Baud Rate/Clock Out modes. All modes increment the timer once per clock cycle. Timer 2 in AutoReload/Capture mode increments at 12 times the rate of standard 8051s. Setting TPS3-0 = 1101B will force Timer 2 to count every twelve clocks. Timer 2 in Baud Rate or Clock Out mode increments at twice the rate of standard 8051s. Setting TPS3-0 = 0001B will force Timer 2 to count every two clocks. 2.3.
AT89LP3240/6440 3. Memory Organization The AT89LP3240/6440 uses a Harvard Architecture with separate address spaces for program and data memory. The program memory has a regular linear address space with support for 64K bytes of directly addressable application code. The data memory has 256 bytes of internal RAM and 128 bytes of Special Function Register I/O space.
Figure 3-1. 01FF Program Memory Map AT89LP3240 01FF AT89LP6440 User Signature Array User Signature Array 0100 0100 007F 007F SIGEN=1 Atmel Signature Array Atmel Signature Array 0000 0000 FFFF Program Memory 7FFF SIGEN=0 Program Memory 0000 0000 3.2 Internal Data Memory The AT89LP3240/6440 contains 256 bytes of general SRAM data memory plus 128 bytes of I/O memory mapped into a single 8-bit address space. Access to the internal data memory does not require any configuration.
AT89LP3240/6440 3.2.2 IDATA The full 256 byte internal RAM can be indirectly addressed using the 8-bit pointers R0 and R1. The first 128 bytes of IDATA include the DATA space. The hardware stack is also located in the IDATA space when XSTK = 0. 3.2.3 SFR The upper 128 direct addresses (80H–FFH) access the I/O registers. I/O registers on AT89LP devices are referred to as Special Function Registers. The SFRs can only be accessed through direct addressing. All SFR locations are not implemented.
Some internal data memory spaces are mapped into portions of the XDATA address space. In this case the lower address ranges will access internal resources instead of external memory. A d d r e s s e s a b o v e t h e ra n g e i m p l e m e n t e d i n t e r na l l y w i l l d e f a u l t t o X D A TA . T h e AT89LP3240/6440 supports up to 52K or 60K bytes of external memory when using the internally mapped memories. Setting the EXRAM bit (AUXR.
AT89LP3240/6440 To enable write access to the nonvolatile data memory, the MWEN bit (MEMCON.4) must be set to one. When MWEN = 1 and DMEN = 1, MOVX @DPTR,A may be used to write to FDATA. FDATA uses flash memory with a page-based programming model. Flash data memory differs from traditional EEPROM data memory in the method of writing data. EEPROM generally can update a single byte with any value. Flash memory splits programming into write and erase operations. A Flash write can only program zeroes, i.
Figure 3-5. FDATA Byte Write DMEN MWEN LDPG IDLE tWC tWC MOVX Figure 3-6. FDATA Page Write DMEN MWEN LDPG IDLE tWC MOVX Frequently just a few bytes within a page must be updated while maintaining the state of the other bytes. There are two options for handling this situation that allow the Flash Data memory to emulate a traditional EEPROM memory.
AT89LP3240/6440 Table 3-3. MEMCON – Memory Control Register MEMCON = 96H Reset Value = 0000 00XXB Not Bit Addressable Bit IAP AERS LDPG MWEN DMEN ERR – WRTINH 7 6 5 4 3 2 1 0 Symbol Function IAP In-Application Programming Enable. When IAP = 1 and the IAP Fuse is enabled, programming of the CODE/SIG space is enabled and MOVX @DPTR instructions will access CODE/SIG instead of EDATA or FDATA. Clear IAP to disable programming of CODE/SIG and allow access to EDATA and FDATA.
Figure 3-8 shows a hardware configuration for accessing 256-byte blocks of external RAM using an 8-bit paged address. Port 0 serves as a multiplexed address/data bus to the RAM. The ALE strobe is used to latch the address byte into an external register so that Port 0 can be freed for data input/output. The Port 2 I/O lines (or other ports) can provide control lines to page the memory; however, this operation is not handled automatically by hardware.
AT89LP3240/6440 automatically tristated when inputting data regardless of the Port 0 configuration. The Port 0 configuration will determine the idle state of Port 0 when not accessing the external memory. Figure 3-9 and Figure 3-10 show examples of external data memory write and read cycles, respectively. The address on P0 and P2 is stable at the falling edge of ALE. The idle polarity of ALE is controlled by ALES (AUXR.0). When ALES = 0 the idle polarity of ALE is high (active).
Figure 3-11. MOVX with One Wait State (WS = 01B) S1 S2 S3 W1 S4 CLK ALE P2 P2 SFR DPH or P2 OUT P2 SFR WR P0 P0 SFR DPL OUT P0 SFR DPL OUT DATA OUT P0 SFR RD P0 FLOAT P0 SFR Figure 3-12. MOVX with Two Wait States (WS = 10B) S1 S2 S3 W1 W2 S4 CLK ALE P2 P2 SFR DPH or P2 OUT P2 SFR WR P0 P0 SFR DPL OUT P0 SFR DPL OUT DATA OUT P0 SFR RD P0 FLOAT P0 SFR Figure 3-13.
AT89LP3240/6440 tain separate copies of SP for use with each stack space. Interrupts should be disabled while swapping copies of SP in such an application to prevent illegal stack accesses. All interrupt calls and PUSH, POP, ACALL, LCALL, RET and RETI instructions will incur a one or two-cycle penalty while the extended stack is enabled, depending on the number of stack access in each instruction. The extended stack may only exist within the internal EDATA space; it cannot be placed in XDATA.
4. Special Function Registers A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 4-1. See also “Register Index” on page 153. Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.
AT89LP3240/6440 5. Enhanced CPU The AT89LP3240/6440 uses an enhanced 8051 CPU that runs at 6 to 12 times the speed of standard 8051 devices (or 3 to 6 times the speed of X2 8051 devices). The increase in performance is due to two factors. First, the CPU fetches one instruction byte from the code memory every clock cycle. Second, the CPU uses a simple two-stage pipeline to fetch and execute instructions in parallel. This basic pipelining concept allows the CPU to obtain up to 1 MIPS per MHz.
Figure 5-3. Two-cycle ALU Operation (Example: ADD A, #data) T1 T2 T3 System Clock Total Execution Time Fetch Immediate Operand ALU Operation Execute Result Write Back Fetch Next Instruction 5.1 Multiply–Accumulate Unit (MAC) The AT89LP3240/6440 includes a multiply and accumulate (MAC) unit that can significantly speed up many mathematical operations required for digital signal processing.
AT89LP3240/6440 The MAC operation is performed by executing the MAC AB (A5 A4H) extended instruction. This two-byte instruction requires nine clock cycles to complete. The operand registers are not modified by the instruction and the result is stored in the 40-bit M register. MAC AB also updates the C and OV flags in PSW. C represents the sign of the MAC result and OV is the two’s complement overflow. Note that MAC AB will not clear OV if it was previously set to one.
Table 5-1. DSPR – Digital Signal Processing Configuration Register DSPR = E2H Reset Value = 0000 0000B Not Bit Addressable Bit MRW1 MRW0 SMLB SMLA CBE1 CBE0 MVCD DPRB 7 6 5 4 3 2 1 0 Symbol Function MRW1-0 M Register Window. Selects which pair of bytes from the 5-byte M register is accessible through MACH (E5H) and MACL (E4H) as shown in Figure 5-5. For example, MRW = 10B for normal 16-bit fixed-point operations where the lowest order portion of the fractional result is discarded.
AT89LP3240/6440 A summary of data pointer instructions with fast context switching is listed inTable 5-2. Table 5-2. Data Pointer Instructions Operation 5.2.
Table 5-5. DPCF – Data Pointer Configuration Register DPCF = A2H Reset Value = 0000 00X0B Not Bit Addressable Bit DPU1 DPU0 DPD1 DPD0 SIGEN 0 – DPS 7 6 5 4 3 2 1 0 Symbol Function DPU1 Data Pointer 1 Update. When set, MOVX @DPTR and MOVC @DPTR instructions that use DPTR1 will also update DPTR1 based on DPD1. If DPD1 = 0 the operation is post-increment and if DPD1 = 1 the operation is post-decrement. When DPU1 = 0, DPTR1 is not updated. DPU0 Data Pointer 0 Update.
AT89LP3240/6440 5.2.2.2 Index Disable The MOVC Index Disable bit, MVCD (DSPR.1), disables the indexed addressing mode of the MOVC A, @A+DPTR instruction. When MVCD = 1, the MOVC instruction functions as MOVC A, @DPTR with no indexing as shown in Table 5-7. MVCD can improve the efficiency of routines that must fetch multiple operands from program memory. DPRB can change the MOVC destination register from ACC to B, but has no effect on the MOVC index register. Table 5-7.
5.3 Instruction Set Extensions Table 5-8 lists the additions to the 8051 instruction set that are supported by the AT89LP3240/6440. For more information on the instruction set see Section 22. “Instruction Set Summary” on page 143. For detailed descriptions of the extended instructions see Section 22.1 “Instruction Set Extensions” on page 147. Table 5-8.
AT89LP3240/6440 6. System Clock The system clock is generated directly from one of three selectable clock sources. The three sources are the on-chip crystal oscillator, external clock source, and internal RC oscillator. The on-chip crystal oscillator may also be configured for low or high speed operation. The clock source is selected by the Clock Source User Fuses as shown in Table 6-1. See “User Configuration Fuses” on page 164.
6.2 External Clock Source The external clock option disables the oscillator amplifier and allows XTAL1 to be driven directly by an external clock source as shown in Figure 6-2. XTAL2 may be left unconnected, used as general purpose I/O P4.1, or configured to output a divided version of the system clock. Figure 6-2. External Clock Drive Configuration NC, GPIO, or CLKOUT XTAL2 (P4.1) EXTERNAL OSCILLATOR SIGNAL XTAL1 (P4.0) GND 6.
AT89LP3240/6440 pass through intermediate frequencies. When CDV is updated, the new frequency will take affect within a maximum period of 128 x tOSC. Table 6-2. CLKREG – Clock Control Register CLKREG = 8FH Reset Value = 0000 0000B Not Bit Addressable Bit Symbol TPS[3-0] TPS3 TPS2 TPS1 TPS0 CDV2 CDV1 CDV0 COE 7 6 5 4 3 2 1 0 Function Timer Prescaler. The Timer Prescaler selects the time base for Timer 0, Timer 1, Timer 2 and the Watchdog Timer.
generated reset can be extended beyond the power-on period by holding the RST pin low longer than the time-out. Figure 7-1. Power-on Reset Sequence (BOD Disabled) VPOR VDD VPOR tPOR + tSUT Time-out RST (RST Tied to VCC) Internal Reset RST VIH (RST Controlled Externally) Internal Reset tRHD If the Brown-out Detector (BOD) is also enabled, the start-up timer does not begin counting until after VDD reaches the BOD threshold voltage VBOD as shown in Figure 7-2.
AT89LP3240/6440 meet the minimum system requirements before the device exits reset and starts normal operation. The RST pin may be held low externally until these conditions are met. Table 7-1.
Note: 7.4 During a power-up sequence, the fuse selection is always overridden and therefore the pin will always function as a reset input. An external circuit connected to this pin should not hold this pin LOW during a power-on sequence if the pin will be configured as a general I/O, as this will keep the device in reset until the pin transitions high. After the power-up delay, this input will function either as an external reset input or as a digital input as defined by the fuse bit.
AT89LP3240/6440 . Table 8-1. PCON – Power Control Register PCON = 87H Reset Value = 000X 0000B Not Bit Addressable Bit SMOD1 SMOD0 PWDEX POF GF1 GF0 PD IDL 7 6 5 4 3 2 1 0 Symbol Function SMOD1 Double Baud Rate bit. Doubles the baud rate of the UART in Modes 1, 2, or 3. SMOD0 Frame Error Select. When SMOD0 = 1, SCON.7 is SM0. When SMOD0 = 1, SCON.7 is FE. Note that FE will be set after a frame error regardless of the state of SMOD0. PWDEX Power-down Exit Mode.
Figure 8-1. Interrupt Recovery from Power-down (PWDEX = 0) PWD XTAL1 tSUT INT1 Internal Clock When PWDEX = “1”, the wake-up period is controlled externally by the interrupt. Again, at the falling edge on the interrupt pin, power-down is exited and the oscillator is restarted. However, the internal clock will not propagate until the rising edge of the interrupt pin as shown in Figure 82. The interrupt pin should be held low long enough for the selected clock source to stabilize.
AT89LP3240/6440 Figure 8-3. Reset Recovery from Power-down PWD XTAL1 tSUT RST Internal Clock Internal Reset 8.3.2 Analog Comparators The comparators will operate during Idle mode if enabled. To save power, the comparators should be disabled before entering Idle mode if possible. When the comparators are turned off and on again, some settling time is required for the analog circuits to stabilize.
The IPxD bits located at the seventh bit of IP, IPH, IP2 and IP2H can be used to disable all interrupts of a given priority level, allowing software implementations of more complex interrupt priority handling schemes such as level-based round-robin scheduling. The External Interrupts INT0 and INT1 can each be either level-activated or edge-activated, depending on bits IT0 and IT1 in Register TCON. The flags that actually generate these interrupts are the IE0 and IE1 bits in TCON.
AT89LP3240/6440 Table 9-1. 9.
rupt system, the response time is always more than 5 clock cycles and less than 21 clock cycles. See Figure 9-1 and Figure 9-2. Figure 9-1. Minimum Interrupt Response Time Clock Cycles 1 5 INT0 IE0 Instruction Figure 9-2. Ack. Cur. Instr. LCALL 1st ISR Instr. Maximum Interrupt Response Time Clock Cycles 1 6 15 21 INT0 Ack. IE0 Instruction Table 9-2. RETI MAC AB LCALL 1st ISR Instr.
AT89LP3240/6440 Table 9-3. IE2 – Interrupt Enable 2 Register IE = B4H Reset Value = xxxx x000B Not Bit Addressable Bit – – – ETWI EADC ESPI ECC EGP 7 6 5 4 3 2 1 0 Symbol Function ETWI Two-Wire Interface Interrupt Enable EADC ADC Interrupt Enable ESPI Serial Peripheral Interface Interrupt Enable ECC Compare/Capture Array Interrupt Enable EGP General-purpose Interrupt Enable Table 9-4.
Symbol Function PSP Serial Peripheral Interface Interrupt Priority Low PCC Compare/Capture Array Interrupt Priority Low PGP General-purpose Interrupt 0 Priority Low Table 9-6. IPH – Interrupt Priority High Register IPH = B7H Reset Value = 0000 0000B Not Bit Addressable Bit IP1D PCH PT2H PSH PT1H PX1H PT0H PX0H 7 6 5 4 3 2 1 0 Symbol Function IP1D Interrupt Priority 1 Disable. Set IP1D to 1 to disable all interrupts with priority level one.
AT89LP3240/6440 10. I/O Ports The AT89LP3240/6440 can be configured for between 35 and 38 I/O pins. The exact number of I/O pins available depends on the clock and reset options as shown in Table 10-1. Table 10-1. I/O Pin Configurations Clock Source Reset Option Number of I/O Pins External Crystal or Resonator External RST Pin 35 No external reset 36 External RST Pin 36 No external reset 37 External RST Pin 37 No external reset 38 External Clock Internal RC Oscillator 10.
10.1.1 Quasi-bidirectional Output Port pins in quasi-bidirectional output mode function similar to standard 8051 port pins. A Quasibidirectional port can be used both as an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. When the pin is driven low, it is driven strongly and able to sink a large current.
AT89LP3240/6440 Figure 10-3. Input Circuit for P3.2, P3.3, P4.0, P4.1 and P4.2 Input Data 10.1.3 Port Pin Open-drain Output The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port pin when the port latch contains a logic “0”. To be used as a logic output, a port configured in this manner must have an external pull-up, typically a resistor tied to VDD. The pulldown for this mode is the same as for the quasi-bidirectional mode.
10.2 Port Analog Functions The AT89LP3240/6440 incorporates two analog comparators and an 8-channel analog-to-digital converter. In order to give the best analog performance and minimize power consumption, pins that are being used for analog functions must have both their digital outputs and digital inputs disabled. Digital outputs are disabled by putting the port pins into the input-only mode as described in “Port Configuration” on page 45.
AT89LP3240/6440 10.4 Port Alternate Functions Most general-purpose digital I/O pins of the AT89LP3240/6440 share functionality with the various I/Os needed for the peripheral units. Table 10-6 lists the alternate functions of the port pins. Alternate functions are connected to the pins in a logic AND fashion. In order to enable the alternate function on a port pin, that pin must have a “1” in its corresponding port register bit, otherwise the input/output will always be “0”.
Table 10-6. Port Pin Alternate Functions Configuration Bits 50 Alternate Function Port Pin PxM0.y PxM1.y P1.2 P1M0.2 P1M1.2 P1.3 P1M0.3 P1M1.3 P1.4 P1M0.4 P1M1.4 P1.5 P1M0.5 P1M1.5 P1.6 P1M0.6 P1M1.6 P1.7 P1M0.7 P1M1.7 P2.0 P2M0.0 P2M1.0 CCA P2.1 P2M0.1 P2M1.1 CCB P2.2 P2M0.2 P2M1.2 P2.3 P2M0.3 P2M1.3 P2.4 P2M0.4 P2.5 SDA Notes open-drain GPI2 SCL open-drain GPI3 SS GPI4 MOSI GPI5 MISO GPI6 SCK GPI7 CCC DA+ input-only CCD DA- input-only P2M1.
AT89LP3240/6440 11.
11.1 Mode 0 – Variable Width Timer/Counter Both Timers in Mode 0 are 8-bit Counters with a variable prescaler. The prescaler may vary from 1 to 8 bits depending on the PSC bits in TCONB, giving the timer a range of 9 to 16 bits. By default the timer is configured as a 13-bit timer compatible to Mode 0 in the standard 8051. Figure 11-1 shows the Mode 0 operation as it applies to Timer 1 in 13-bit mode. As the count rolls over from all “1”s to all “0”s, it sets the Timer interrupt flag TF1.
AT89LP3240/6440 Figure 11-2. Timer/Counter 1 Mode 1: 16-bit Auto-Reload RL1 (8 Bits) RH1 (8 Bits) ÷TPS OSC Reload C/T = 0 TL1 (8 Bits) TH1 (8 Bits) TF1 Interrupt C/T =1 T1 Pin Control TR1 GATE1 INT1 Pin 11.3 Mode 2 – 8-bit Auto-Reload Timer/Counter Mode 2 configures the Timer register as an 8-bit Counter (TL1) with automatic reload, as shown in Figure 11-3. Overflow from TL1 not only sets TF1, but also reloads TL1 with the contents of TH1, which is preset by software.
Mode 3 is for applications requiring an extra 8-bit timer or counter. With Timer 0 in Mode 3, the AT89LP3240/6440 can appear to have four Timer/Counters. When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3. In this case, Timer 1 can still be used by the serial port as a baud rate generator or in any application not requiring an interrupt. Figure 11-4.
AT89LP3240/6440 Table 11-3. TMOD – Timer/Counter Mode Control Register TMOD Address = 089H Reset Value = 0000 0000B Not Bit Addressable Bit GATE1 C/T1 T1M1 T1M0 GATE0 C/T0 T0M0 T0M1 7 6 5 4 3 2 1 0 Symbol Function GATE1 Timer 1 Gating Control. When set, Timer/Counter 1 is enabled only while INT1 pin is high and TR1 control pin is set. When cleared, Timer 1 is enabled whenever TR1 control bit is set. C/T1 Timer or Counter Selector 1.
Table 11-4. TCONB – Timer/Counter Control Register B TCONB = 91H Reset Value = 0010 0100B Not Bit Addressable Bit PWM1EN PWM0EN PSC12 PSC11 PSC10 PSC02 PSC01 PSC00 7 6 5 4 3 2 1 0 Symbol Function PWM1EN Configures Timer 1 for Pulse Width Modulation output on T1 (P3.5). PWM0EN Configures Timer 0 for Pulse Width Modulation output on T0 (P3.4). PSC12 PSC11 PSC10 Prescaler for Timer 1 Mode 0. The number of active bits in TL1 equals PSC1 + 1.
AT89LP3240/6440 11.5.1 Mode 0 – 8-bit PWM with 8-bit Logarithmic Prescaler In Mode 0, TLx acts as a logarithmic prescaler driving 8-bit counter THx (see Figure 11-6). The PSCx bits in TCONB control the prescaler value. On THx overflow, the duty cycle value in RHx is transferred to OCRx and the output pin is set high. When the count in THx matches OCRx, the output pin is cleared low. The following formulas give the output frequency and duty cycle for Timer 0 in PWM Mode 0.
Figure 11-7. Timer/Counter 1 PWM Mode 1 RH1 (8 Bits) RL1 (8 Bits) OCR1 = T1 OSC TH1 (8 Bits) TL1 (8 Bits) ÷TPS Control TR1 GATE1 INT1 Pin Figure 11-8. Timer/Counter 1 PWM Mode 2 TH1 (8 Bits) OSC TL1 (8 Bits) ÷TPS T1 Control TR1 GATE1 INT1 Pin Note: {RH0 & RL0}/{RH1 & RL1} are not required by Timer 0/Timer 1 during PWM Mode 2 and may be used as temporary storage registers. Figure 11-9.
AT89LP3240/6440 11.5.4 Mode 3 – Split 8-bit PWM Timer 1 in PWM Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in PWM Mode 3 establishes TL0 and TH0 as two separate PWM counters in a manner similar to normal Mode 3. PWM Mode 3 on Timer 0 is shown in Figure 11-10. Only the Timer Prescaler is available to change the output frequency during PWM Mode 3. TL0 can use the Timer 0 control bits: GATE, TR0, INT0, PWM0EN and TF0.
12. Enhanced Timer 2 The AT89LP3240/6440 includes a 16-bit Timer/Counter 2 with the following features: • 16-bit timer/counter with one 16-bit reload/capture register • One external reload/capture input • Up/Down counting mode with external direction control • UART baud rate generation • Output-pin toggle on timer overflow • Dual slope symmetric operating modes Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter.
AT89LP3240/6440 12.1 Timer 2 Registers Control and status bits for Timer 2 are contained in registers T2CON (see Table 12-3) and T2MOD (see Table 12-4). The register pair {TH2, TL2} at addresses 0CDH and 0CCH are the 16-bit timer register for Timer 2. The register pair {RCAP2H, RCAP2L} at addresses 0CBH and 0CAH are the 16-bit Capture/Reload register for Timer 2 in capture and auto-reload modes. Table 12-3.
Symbol Function PHS [2-0] CCA Phase Mode. PWM channels may be grouped by 2, 3 or 4 such that only one channel in a group produces a pulse in any one period. The PHS[2-0] bits may only be written when the timer is not active, i.e. TR2 = 0.
AT89LP3240/6440 Figure 12-1. Timer 2 Diagram: Capture Mode OSC ÷TPS C/T2 = 0 TL2 TH2 TF2 OVERFLOW C/T2 = 1 TR2 CAPTURE T2 PIN RCAP2L RCAP2H TRANSITION DETECTOR TIMER 2 INTERRUPT T2EX PIN EXF2 EXEN2 12.3 Auto-Reload Mode Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD (see Table 12-4). Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up.
RCAP2L and then overflows. The overflow sets TF2 and causes the timer registers to be reloaded with MIN. If EXEN2 = 1, a 1-to-0 transition on T2EX will clear the timer and set EXF2.
AT89LP3240/6440 registers, TH2 and TL2, respectively. A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal BOTTOM, the 16-bit value stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes MAX to be reloaded into the timer registers. The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt.
Figure 12-6. Timer 2 Waveform: Auto-Reload Mode (DCEN = 1) TF2 Set MAX BOTTOM MIN T2CM1-0 = 00B, DCEN = 1 T2EX EXF2 MAX TF2 Set TOP MIN T2CM1-0 = 01B, DCEN = 1 12.3.3 66 Dual Slope Counter When Timer 2 Auto-Reload Mode uses Count Mode 2 (T2CM 1-0 = 10B) or Count Mode 3 (T2CM1-0 = 11B), the timer operates in a dual slope fashion. The timer counts up from MIN to TOP and then counts down from TOP to MIN, following a sawtooth waveform as shown in Figure 12-7.
AT89LP3240/6440 Figure 12-7. Timer 2 Waveform: Dual Slope Modes MAX T2CM1-0 = 10B TF2 Set TOP MIN EXF2 MAX T2CM1-0 = 11B TF2 Set TOP MIN 12.4 Baud Rate Generator Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Table 12-3). Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or transmitter and Timer 1 is used for the other function.
erator, T2EX can be used as an extra external interrupt. Also note that the Baud Rate and Frequency Generator modes may be used simultaneously. Figure 12-8. Timer 2 in Baud Rate Generator Mode TIMER 1 OVERFLOW ÷2 "0" OSC ÷TPS "1" SMOD1 C/T2 = 0 "1" TL2 "0" TH2 RCLK ÷16 TR2 Rx CLOCK C/T2 = 1 "1" "0" T2 PIN RCAP2L TCLK RCAP2H TRANSITION DETECTOR ÷ 16 T2EX PIN EXF2 Tx CLOCK TIMER 2 INTERRUPT EXEN2 12.
AT89LP3240/6440 Figure 12-9. Timer 2 in Clock-out Mode OSC ÷TPS TL2 TH2 RCAP2L RCAP2H TR2 C/T2 T2OE ÷2 T2 PIN T2EX PIN EXF2 TRANSITION DETECTOR TIMER 2 INTERRUPT EXEN2 13. Compare/Capture Array The AT89LP3240/6440 includes a four channel Compare/Capture Array (CCA) that performs a variety of timing operations including input event capture, output compare waveform generation and pulse width modulation (PWM). Timer 2 serves as the time base for the four 16-bit compare/capture modules.
Figure 13-1. Compare/Capture Array Block Diagram OSC ÷TPS RCAP2L RCAP2H TL2 TH2 C/T2 = 0 (P1.0) T2 C/T2 =1 TF2 T2CCF Timer 2 Interrupt CCA Interrupt TR2 CCCA CCAL CCAH CCA (P2.0) CCCB CCBL CCBH CCB (P2.1) CCCC CCCL CCCH CCC (P2.2) CCCD CCDL CCDH CCD (P2.3) T2CCC T2CCL T2CCH T2CCA 13.1 CCA Registers The Compare/Capture Array has five Special Function Registers: T2CCA, T2CCC, T2CCL, T2CCH and T2CCF. The T2CCF register contains the interrupt flags for each CCA channel.
AT89LP3240/6440 Table 13-1. T2CCA – Timer/Counter 2 Compare/Capture Address T2CCA Address = 0D1H Reset Value = xxxx xx00B Not Bit Addressable — — — — — — T2CCA.1 T2CCA.0 Bit 7 6 5 4 3 2 1 0 Symbol Function Compare/Capture Address. Selects which CCA channel is currently accessible through the T2CCH, T2CCL and T2CCC registers. Only one channel may be accessed at a time.
Table 13-4. T2CCF – Timer/Counter 2 Compare/Capture Flags T2CCF Address = 0D5H Reset Value = XXXX 0000B Not Bit Addressable – – – – CCFD CCFC CCFB CCFA Bit 7 6 5 4 3 2 1 0 Symbol Function CCFD Channel D Compare/Capture Interrupt Flag. Set by a compare/capture event on channel D. Must be cleared by software. CCFD will generate an interrupt when CIEND = 1 and ECC = 1. CCFC Channel C Compare/Capture Interrupt Flag. Set by a compare/capture event on channel C.
AT89LP3240/6440 to occur at a negative edge, positive edge, or both (toggle). Capture inputs are sampled every clock cycle and a new value must be held for at least 2 clock cycles to be correctly sampled by the device. The maximum achievable capture rate will be determined by how fast the software can retrieve the captured data. There is no protection against capture events overrunning the data register.
Table 13-5. T2CCC – Timer/Counter 2 Compare/Capture Control T2CCC Address = 0D4H Reset Value = 00X0 0000B Not Bit Addressable CIENx CDIRx – CTCx CCMx CxM2 CxM1 CxM0 Bit 7 6 5 4 3 2 1 0 Symbol Function CIENx Channel X Interrupt Enable. When set, channel X’s interrupt flag, CCFx in T2CCF, will generate an interrupt when ECC = 1. Clear to disable interrupts from channel X. CDIRx Channel X Capture Direction.
AT89LP3240/6440 13.3 Output Compare Mode The Compare/Capture Array provides a variety of compare modes suitable for event timing or waveform generation. CCA channels are configured for compare mode by setting the CCMx bit in the associated CCCx register to 1. A compare event occurs when the 16-bit contents of a channel’s data register match the contents of Timer 2 (TH2 and TL2).
13.3.1.1 Normal Mode The simplest waveform mode is when CP/RL2 = 0 and T2CM1-0 = 01B. In this mode the frequency of the output is determined by the TOP value stored in RCAP2L and RCAP2H and output edges occur at fractions of the timer period. Figure 13-4 shows an example of outputting two waveforms of the same frequency but different phase by using the toggle on match action. More complex waveforms are achieved by changing the TOP value and the compare values more frequently. Figure 13-4.
AT89LP3240/6440 Figure 13-6. Dual-Slope Waveform Example CP/RL2 = 0, T2CM1-0 = 10B, DCEN = 0 {RCAP2H,RCA2L} {CCAH,CCAL} {CCBH,CCBL} CCA CCB 13.3.2 13.4 Timer 2 Operation for Compare Mode Compare channels will work with any Timer 2 operating mode. The full 16-bit compare range may not be available in all modes. In order for a compare output action to take place, the compare values must be within the counting range of Timer 2.
13.4.1 Asymmetrical PWM For Asymmetrical PWM, Timer 2 should be configured for Auto-Reload mode and Count Mode 1 (CP/RL2 = 0, DCEN = 0, T2CM1-0 = 01B). Asymmetrical PWM uses single slope operation as shown in Figure 13-8. The timer counts up from BOTTOM to TOP and then restarts from BOTTOM. In non-inverting mode, the output CCx is set on the compare match between Timer 2 (TL2, TH2) and the channel data register (CCxL, CCxH), and cleared at BOTTOM.
AT89LP3240/6440 center-aligned around the timer equal to TOP point. Symmetrical PWM may be used to generate non-overlapping waveforms. The TOP value in RCAP2L and RCAP2H is double buffered such that the output frequency is only updated at the underflow. The channel data register (CCxL, CCxH) is also double-buffered to prevent glitches.
Figure 13-10. Phase and Frequency Correct Symmetrical (Center-Aligned) PWM CP/RL2 = 0, T2CM1-0 = 10B, DCEN = 0 Duty Cycle Updated {RCAP2H,RCA2L} {CCxH,CCxL} Inverted CCx Non-Inverted Figure 13-11. Phase Correct Symmetrical (Center-Aligned) PWM CP/RL2 = 0, T2CM1-0 = 11B, DCEN = 0 Duty Cycle Updated {RCAP2H,RCA2L} {CCxH,CCxL} Inverted CCx Non-Inverted 13.4.3 Multi-Phasic PWM The PWM channels may be configured to provide multi-phasic alternating outputs by the PHS2-0 bits in T2MOD.
AT89LP3240/6440 Table 13-6. Summary of Multi-Phasic Modes Behavior PHS2-0 Mode PHSD = 0 PHSD = 1 000 Off 001 1:2 A →B →A →B B →A →B →A 010 1:3 A →B →C →A →B →C C →B →A →C →B →A 011 1:4 100 2:4 A →B →C →D →A →B →C →D A →B →A →B C →D →C →D D →C →B →A →D →C →B →A B →A →B →A D →C →D →C Normal Operation (all channels active at all times) Figure 13-12.
Figure 13-14. Multi-Phasic PWM Modes PHS = 000B CCA CCB CCC CCD PHS = 001B CCA CCB CCC CCD PHS = 010B CCA CCB CCC CCD PHSD PHS = 011B CCA CCB CCC CCD PHSD PHS = 100B CCA CCB CCC CCD 14. External Interrupts The INT0 (P3.2) and INT1 (P3.3) pins of the AT89LP3240/6440 may be used as external interrupt sources. The external interrupts can be programmed to be level-activated or transitionactivated by setting or clearing bit IT1 or IT0 in Register TCON.
AT89LP3240/6440 another interrupt will be generated. Both INT0 and INT1 may wake up the device from the Power-down state. 15. General-purpose Interrupts The General-purpose Interrupt (GPI) function provides 8 configurable external interrupts on Port 1. Each port pin can detect high/low levels or positive/negative edges. The GPIEN register select which bits of Port 1 are enabled to generate an interrupt. The GPMOD and GPLS registers determine the mode for each individual pin.
. Table 15-1. GPMOD – General-purpose Interrupt Mode Register GPMOD = 9AH Reset Value = 0000 0000B Not Bit Addressable GPMOD7 GPMOD6 GPMOD5 GPMOD4 GPMOD3 GPMOD2 GPMOD1 GPMOD0 7 6 5 4 3 2 1 0 Bit GPMOD.x 0 = level-sensitive interrupt for P1.x 1 = edge-triggered interrupt for P1.x Table 15-2.
AT89LP3240/6440 16. Serial Interface (UART) The serial interface on the AT89LP3240/6440 implements a Universal Asynchronous Receiver/Transmitter (UART).
bit and prepares to receive the data bytes that follows. The slaves that are not addressed set their SM2 bits and ignore the data bytes. See “Automatic Address Recognition” on page 97. The SM2 bit can be used to check the validity of the stop bit in Mode 1. In a Mode 1 reception, if SM2 = 1, the receive interrupt is not activated unless a valid stop bit is received. Table 16-1.
AT89LP3240/6440 16.2 Baud Rates The baud rate in Mode 0 depends on the value of the SMOD1 bit in Special Function Register PCON.7. If SMOD1 = 0 (the value on reset) and TB8 = 0, the baud rate is 1/4 of the oscillator frequency. If SMOD1 = 1 and TB8 = 0, the baud rate is 1/2 of the oscillator frequency, as shown in the following equation: Mode 0 Baud Rate TB8 = 0 SMOD1 2 = -------------------- × Oscillator Frequency 4 The baud rate in Mode 2 also depends on the value of the SMOD1 bit.
Table 16-2. Commonly Used Baud Rates Generated by Timer 1 (TPS = 0000B) Timer 1 16.2.2 Baud Rate fOSC (MHz) SMOD1 C/T Mode Reload Value Mode 0: 1 MHz 4 0 X X X Mode 2: 750K 12 1 X X X 62.5K 12 1 0 2 F4H 38.4K 11.059 0 0 2 F7H 19.2K 11.059 1 0 2 DCH 9.6K 11.059 0 0 2 DCH 4.8K 11.059 0 0 2 B8H 2.4K 11.059 0 0 2 70H 1.2K 11.059 0 0 1 FEE0H 137.5 11.
AT89LP3240/6440 16.3 More About Mode 0 In Mode 0, the UART is configured as a two wire half-duplex synchronous serial interface. Serial data enters and exits through RXD. TXD outputs the shift clock. Eight data bits are transmitted/received, with the LSB first. Figure 16-1 on page 90 shows a simplified functional diagram of the serial port in Mode 0 and associated timing. The baud rate is programmable to 1/2 or 1/4 the oscillator frequency by setting/clearing the SMOD1 bit.
Figure 16-1.
AT89LP3240/6440 Figure 16-2.
16.4 More About Mode 1 Ten bits are transmitted (through TXD), or received (through RXD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in SCON. In the AT89LP3240/6440, the baud rate is determined either by the Timer 1 overflow rate, the TImer 2 overflow rate, or both. In this case one timer is for transmit and the other is for receive.
AT89LP3240/6440 Figure 16-4. Serial Port Mode 1 TIMER 2 OVERFLOW TIMER 1 OVERFLOW INTERNAL BUS “1” WRITE TO SBUF ÷2 “0” S D Q CL “1” SBUF SMOD1 TXD ZERO DETECTOR “0” “1” SHIFT DATA START TX CONTROL TCLK ÷16 SEND TI SERIAL PORT INTERRUPT “1” “0” RX CLOCK RCLK ÷16 SAMPLE 1-TO-0 TRANSITION DETECTOR RX CLOCK RI START RX CONTROL LOAD SBUF SHIFT 1FFH BIT DETECTOR INPUT SHIFT REG.
16.5 More About Modes 2 and 3 Eleven bits are transmitted (through TXD), or received (through RXD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the 9th data bit (TB8) can be assigned the value of “0” or “1”. On receive, the 9th data bit goes into RB8 in SCON. The baud rate is programmable to either 1/16 or 1/32 of the oscillator frequency in Mode 2.
AT89LP3240/6440 Figure 16-5.
Figure 16-6. Serial Port Mode 3 TIMER 2 OVERFLOW TIMER 1 OVERFLOW INTERNAL BUS TB8 WRITE TO SBUF ÷2 “0” S D Q CL “1” SMOD1 SBUF TXD ZERO DETECTOR “0” “1” TCLK ÷16 “0” SHIFT DATA START STOP BIT TX CONTROL RX CLOCK SEND TI SERIAL PORT INTERRUPT “1” RCLK ÷16 SAMPLE 1-TO-0 TRANSITION DETECTOR RX CLOCK RI START RX CONTROL LOAD SBUF SHIFT 1FFH BIT DETECTOR INPUT SHIFT REG.
AT89LP3240/6440 16.6 Framing Error Detection In addition to all of its usual modes, the UART can perform framing error detection by looking for missing stop bits, and automatic address recognition. When used for framing error detect, the UART looks for missing stop bits in the communication. A missing bit will set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SM0 and the function of SCON.7 is determined by PCON.6 (SMOD0). If SMOD0 is set then SCON.7 functions as FE. SCON.
In a more complex system, the following could be used to select slaves 1 and 2 while excluding slave 0: Slave 0 SADDR = 1100 0000 SADEN = 1111 1001 Given = 1100 0XX0 Slave 1 SADDR = 1110 0000 SADEN = 1111 1010 Given = 1110 0X0X Slave 2 SADDR = 1110 0000 SADEN = 1111 1100 Given = 1110 00XX In the above example, the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110.
AT89LP3240/6440 Figure 17-1. SPI Block Diagram S Oscillator M M T1 OVF 0 MSB TSCK LSB Read Data Buffer Write Data Buffer SPI Clock (Master) SPR0 M SPI Status Register DORD SPR0 SPR1 CPHA CPOL MSTR DORD SPI Control Register 8 SPI Interrupt Request SPE 8 TSCK MSTR SPE ENH SSIG DISSO TXE MODF SPE MSTR SS P1.4 SPI Control WCOL SCK 1.7 S Clock Logic Select SPR1 S 8-bit Shift Register Divider ÷4/÷8/÷32/÷64 SPIF MOSI P1.5 Pin Control Logic 1 MISO P1.
Figure 17-2. SPI Master-Slave Interconnection Master MSB LSB Slave MSB MISO LSB MISO 8-Bit Shift Register 8-Bit Shift Register MOSI MOSI SSIG SS MODF DISSO VCC SS SSIG GPIO Clock Generator SCK SCK When the SPI is configured as a Master (MSTR in SPCR is set), the operation of the SS pin depends on the setting of the Slave Select Ignore bit, SSIG. If SSIG = 1, the SS pin is a general purpose output pin which does not affect the SPI system.
AT89LP3240/6440 and if the ENH bit in SPSR is set. For multi-byte transfers, TXE may be used to remove any dead time between byte transmissions. The SPI master can operate in two modes: multi-master mode and single-master mode. By default, multi-master mode is active when SSIG = 0. In this mode, the SS input is used to disable a master device when another master is accessing the bus.
. Table 17-1.
AT89LP3240/6440 Symbol Function SPI clock rate select. These two bits control the SCK rate of the device configured as master. SPR1 and SPR0 have no effect on the slave. The relationship between SCK and the oscillator frequency, FOSC., is as follows: SPR1 SPR0 0 SPR0 SPR1 Notes: SCK (TSCK = 0) SCK (TSCK = 1) 0 fOSC/4 fT1OVF/4 0 1 fOSC/8 fT1OVF/8 1 0 fOSC/32 fT1OVF/32 1 1 fOSC/64 fT1OVF/64 1.
SSIG Slave Select Ignore. If SSIG = 0, the SPI will only operate in slave mode if SS (P1.4) is pulled low. When SSIG = 1, the SPI ignores SS in slave mode and is active whenever SPE (SPCR.6) is set. When MSTR = 1 and SSIG = 0, SS is monitored for master mode collisions. Setting SSIG = 1 will ignore collisions on SS. P1.4 may be used as a regular I/O pin when SSIG = 1. DISSO Disable slave output bit.
AT89LP3240/6440 18. Two-Wire Serial Interface The Two-Wire Interface (TWI) is a bi-directional 2-wire serial communication standard. It is designed primarily for simple but efficient integrated circuit (IC) control. The system is comprised of two lines, SCL (Serial Clock) and SDA (Serial Data) that carry information between the ICs connected to them. The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines.
18.1 18.1.1 Data Transfer and Frame Format Transferring Bits Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level of the data line must be stable when the clock line is high. The only exception to this rule is for generating start and stop conditions. Figure 18-2. Data Validity SDA SCL Data Stable Data Stable Data Change 18.1.2 START and STOP Conditions The Master initiates and terminates a data transmission.
AT89LP3240/6440 ter’s request, the SDA line should be left high in the ACK clock cycle. The Master can then transmit a STOP condition, or a REPEATED START condition to initiate a new transmission. An address packet consisting of a slave address and a READ or a WRITE bit is called SLA+R or SLA+W, respectively. The MSB of the address byte is transmitted first. Slave addresses can freely be allocated by the designer, but the address 0000 000 is reserved for a general call.
18.1.5 Combining Address and Data Packets Into a Transmission A transmission basically consists of a START condition, a SLA+R/W, one or more data packets and a STOP condition. An empty message, consisting of a START followed by a STOP condition, is illegal. Note that the wired-ANDing of the SCL line can be used to implement handshaking between the Master and the Slave. The Slave can extend the SCL low period by pulling the SCL line low.
AT89LP3240/6440 Figure 18-7. SCL Synchronization between Multiple Masters TA low TA high SCL from Master A SCL from Master B SCL bus Line TBhigh TBlow Masters Start Counting Low Period Masters Start Counting High Period Arbitration is carried out by all masters continuously monitoring the SDA line after outputting data. If the value read from the SDA line does not match the value the master had output, it has lost the arbitration.
It is the user software’s responsibility to ensure that these illegal arbitration conditions never occur. This implies that in multi-master systems, all data transfers must use the same composition of SLA+R/W and data packets. In other words: All transmissions must contain the same number of data packets, otherwise the result of the arbitration is undefined. 18.3 Overview of the TWI Module The TWI module is comprised of several submodules, as shown in Figure 18-9.
AT89LP3240/6440 average TWI bus clock period. The SCL frequency is generated according to the following equation: System Clock SCL frequency = ---------------------------------------------16 × ( TWBR + 1 ) 18.3.3 Bus Interface Unit This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller and Arbitration detection hardware. The TWDR contains the address or data bytes to be transmitted, or the address or data bytes received.
18.4 Register Overview Table 18-1. TWCR – Two-Wire Control Register TWCR Address = AAH Reset Value = X000 00XXB Not Bit Addressable Bit – TWEN STA STO TWIF AA – – 7 6 5 4 3 2 1 0 Symbol Function TWEN Two-wire Serial Interface Enable. Set to enable the TWI. Clear to disable the TWI. STA Start Flag. Set to send a START condition on the bus. Must be cleared by software. STO Stop Flag. Set to send a STOP condition on the bus. Cleared automatically by hardware when the STOP occurs.
AT89LP3240/6440 Table 18-4. TWDR – Two-Wire Data Register TWDR Address = ADH Reset Value = 1111 1111B Not Bit Addressable TWD7 TWD6 TWD5 TWD4 TWD3 TWD2 TWD1 TWD0 7 6 5 4 3 2 1 0 Bit Symbol Function TWD7-0 Two-wire Interface Data. Writes to TWDR queue the next address or data byte for transmission. Reads from TWDR return the last address or data byte present on the bus. Writes/reads to/from TWDR must occur only while TWIF is set. Writes to TWDR while TWIF = 0 are ignored.
Application Action Figure 18-10. Interfacing the Application to the TWI in a Typical Transmission 1. Application writes to TWCR to initiate transmission of START TWI Hardware Action TWI bus 3. Check TWSR to see if START was sent. Application loads SLA+W into TWDR, and loads appropriate control signals into TWCR, making sure that TWIF is written to zero and STA is written to zero. START 2. TWIF set. Status code indicates START condition sent SLA+W 5.
AT89LP3240/6440 long as the TWIF bit in TWCR is set. Immediately after the application has cleared TWIF, the TWI will initiate transmission of the data packet. 6. When the data packet has been transmitted, the TWIF flag in TWCR is set, and TWSR is updated with a status code indicating that the data packet has successfully been sent. The status code will also reflect whether a slave acknowledged the packet or not. 7.
SLA: Slave Address In Figure 18-11 to Figure 18-14, circles are used to indicate that the TWIF flag is set. The numbers in the circles show the status code held in TWSR. At these points, actions must be taken by the application to continue or complete the TWI transfer. The TWI transfer is suspended until the TWIF flag is cleared by software. When the TWIF flag is set, the status code in TWSR is used to determine the appropriate software action.
AT89LP3240/6440 . Table 18-6.
Figure 18-11.
AT89LP3240/6440 TWEN must be written to one to enable the Two-wire Serial Interface, STA must be written to one to transmit a START condition and TWIF must be cleared. The TWI will then test the Twowire Serial Bus and generate a START condition as soon as the bus becomes free. After a START condition has been transmitted, the TWIF flag is set by hardware, and the status code in TWSR will be 08h (see Table 18-7). In order to enter MR mode, SLA+R must be transmitted. This is done by writing SLA+R to TWDR.
Figure 18-12. Format and States in Master Receiver Mode MR Successfull reception from a slave receiver S SLA R A DATA A 40h 08h DATA 50h A P 58h Next transfer started with a repeated start condition RS SLA R 10h Not acknowledge received after the slave address A W P 48h MT Arbitration lost in slave address or data byte A or A Other master continues A 38h Arbitration lost and addressed as slave A 68h From master to slave 18.6.
AT89LP3240/6440 TWEN must be written to one to enable the TWI. The AA bit must be written to one to enable the acknowledgment of the device’s own slave address or the general call address. STA and STO must be written to zero. When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own slave address (or the general call address if enabled) followed by the data direction bit. If the direction bit is “0” (write), the TWI will operate in SR mode, otherwise ST mode is entered.
Table 18-8.
AT89LP3240/6440 18.6.4 Slave Transmitter Mode In the Slave Transmitter mode, a number of data bytes are transmitted to a master receiver. To initiate the Slave Transmitter mode, upper 7 bits of TWAR must be initialized with the address to which the Two-wire Serial Interface will respond when addressed by a master. If the LSB is set, the TWI will respond to the general call address (00h), otherwise it will ignore the general call address. TWEN must be written to one to enable the TWI.
. Table 18-9.
AT89LP3240/6440 18.6.5 Miscellaneous States There are two status codes that do not correspond to a defined TWI state, see Table 18-10. Status F8h indicates that no relevant information is available because the TWIF flag is not set. This occurs between other states, and when the TWI is not involved in a serial transfer. Status 00h indicates that a bus error has occurred during a Two-wire Serial Bus transfer. A bus error occurs when a START or STOP condition occurs at an illegal position in the format frame.
Figure 18-15. Combining Several TWI Modes to Access a Serial EEPROM Master Transmitter S SLA+W A ADDRESS Master Receiver A S = START Rs SLA+R A DATA Rs = REPEATED START Transmitted from master to slave A P P = STOP Transmitted from slave to master 19. Dual Analog Comparators The AT89LP3240/6440 provides two analog comparators. The analog comparators have the following features: • Internal 3-level Voltage Reference (1.2V, 1.3V, 1.
AT89LP3240/6440 also set the CONA (ACSRA.5) or CONB (ACSRB.5) bits to connect the comparator inputs before using a comparator. When a comparator is first enabled, the comparator output and interrupt flag are not guaranteed to be stable for 10 µs. The corresponding comparator interrupt should not be enabled during that time, and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service.
Figure 19-2. Equivalent Analog Input Model RMUX = 10 kΩ RIN = 10 kΩ AINn CPIN = 10 pF 19.2 CCMP < 0.3 pF Internal Reference Voltage The negative input terminal of each comparator may be connected to an internal voltage reference by changing the RFB1-0 or RFA1-0 bits in AREF. The internal reference voltage, VAREF, is set to 1.3 V ±5%. The voltage reference also provides two additional voltage levels approximately 100 mV above and below VAREF.
AT89LP3240/6440 Figure 19-4. Dual Comparator Configuration Examples a. dual independent comparators with external references + AIN0 - AIN1 A AIN3 + AIN2 - CMPA B f. 2-channel window comparator with external reference CMPB - AIN2 CSA = 00 RFA = 00 CSB = 11 RFB = 00 + B CMPB AIN0 b. 3-channel comparator with external reference AIN3 AIN0 + AIN2 AIN1 AIN3 - + A CMPA - AIN1 CSA = 00/10/11 RFA = 00 A CMPA CSA = CSB = 00/11 RFA = RFB = 00 c.
Table 19-1. ACSRA – Analog Comparator A Control & Status Register ACSRA = 97H Reset Value = 0000 0000B Not Bit Addressable Bit CSA1 CSA0 CONA CFA CENA CMA2 CMA1 CMA0 7 6 5 4 3 2 1 0 Symbol Function CSA [1-0] Comparator A Positive Input Channel Select(1) CSA1 CSA0 A+ Channel 0 0 AIN0 (P2.4) 0 1 AIN1 (P2.5) 1 0 AIN2 (P2.6) 1 1 AIN3 (P2.7) CONA Comparator A Input Connect. When CONA = 1 the analog input pins are connected to the comparator.
AT89LP3240/6440 Table 19-2. ACSRB – Analog Comparator B Control & Status Register ACSRB = 9FH Reset Value = 1100 0000B Not Bit Addressable Bit CSB1 CSB0 CONB CFB CENB CMB2 CMB1 CMB0 7 6 5 4 3 2 1 0 Symbol Function CSB [1-0] Comparator B Positive Input Channel Select(1) CSB1 CSB0 B+ Channel 0 0 AIN0 (P2.4) 0 1 AIN1 (P2.5) 1 0 AIN2 (P2.6) 1 1 AIN3 (P2.7) CONB Comparator B Input Connect. When CONB = 1 the analog input pins are connected to the comparator.
Table 19-3. AREF – Analog Comparator Reference Control Register AREF = AFH Reset Value = 0000 0000B Not Bit Addressable Bit CBC1 CBC0 RFB1 RFB0 CAC1 CAC0 RFA1 RFA0 7 6 5 4 3 2 1 0 Symbol Function CSC [1-0] Comparator B Clock Select RFB [1-0] CAC [1-0] RFA [1-0] Notes: CBC1 CBC0 Clock Source 0 0 System Clock 0 0 Timer 0 Overflow 0 1 Timer 1 Overflow 0 1 Timer 2 Overflow Comparator B Negative Input Channel Select(1) CRF1 RFB0 B- Channel 0 0 AIN2 (P2.
AT89LP3240/6440 20. Digital-to-Analog/Analog-to-Digital Converter The AT89LP3240/6440 includes a 10-bit Data Converter (DADC) with the following features: • Digital-to-Analog (DAC) or Analog-to-Digital (ADC) Mode • 10-bit Resolution • 6.5 µs Conversion Time • 8 Multiplexed Single-ended Channels or 4 Differential Channels • Selectable 1.
Table 20-1. Example ADC Conversion Codes Right Adjust Left Adjust Single-Ended Mode (VIN) Differential Mode (VIN+ – VIN-) 0 0 VDD/2 0 0100h 4000h VDD/2 + 1/2 x VREF 1/2 x VREF 01FFh 7FC0h VDD/2 + 511/512 x VREF 511/512 x VREF FF00h C000h VDD/2 – 1/2 x VREF –1/2 x VREF FE01h 8040h VDD/2 – 511/512 x VREF –511/512 x VREF Figure 20-1.
AT89LP3240/6440 20.1 ADC Operation The ADC converts an analog input voltage to a 10-bit signed digital value through successive approximation. When DIFF (DADI.3) is zero, the ADC operates in single-ended mode and the input voltage is the difference between the voltage at the input pin and VDD/2. In differential mode (DIFF = 1) the input voltage is the difference between the positive and negative input pins.
Figure 20-3. Equivalent Analog Input Model RIN = 10 kΩ RMUX = 10 kΩ ADCn CPIN = 10 pF 20.2 CS/H = 2 pF DAC Operation The DAC converts a 10-bit signed digital value to an analog output current through successive approximation. The DAC always operates in differential mode, outputting a differential current between its positive (P2.2) and negative (P2.3) outputs with a common mode voltage of VDD/2.
AT89LP3240/6440 Figure 20-5. Equivalent Analog Output Model ROUT = 100 kΩ DAn CPIN = 10 pF VOUT AVDD/2 20.3 Clock Selection The DADC requires a clock of 2 MHz or less to achieve full resolution. By default the DADC will use an internal 2 MHz clock generated from the 8 MHz internal oscillator. The internal oscillator will be enabled even if it is not supplying the system clock. This may result in higher power consumption.
be set by hardware while the conversion is in progress. Note that the timer overflow rate must be slower than the conversion time. 20.5 Noise Considerations Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: • Connect a decoupling capacitor between the VDD pin and GND as shown in Figure 20-7.
AT89LP3240/6440 Table 20-2. DADC – DADC Control Register DADC = D9H Reset Value = 0000 0000B Not Bit Addressable ADIF GO/BSY DAC ADCE LADJ ACK2 ACK1 ACK0 7 6 5 4 3 2 1 0 Bit Symbol Function ADIF ADC Interrupt Flag. Set by hardware when a conversion completes. Cleared by hardware when calling the interrupt service routine. GO/BSY Conversion Start/Busy Flag. In software triggered mode, writing a 1 to this bit starts a conversion.
Table 20-5. DADI – DADC Input Control Register DADI = DAH Reset Value = 0000 0000B Not Bit Addressable ACON IREF TRG1 TRG0 DIFF ACS2 ACS1 ACS0 7 6 5 4 3 2 1 0 Bit Symbol Function ACON Analog Input Connect. When cleared, the analog inputs are disconnected from the ADC. When set, the analog inputs selected by ACS2-0 are connected to the ADC. ACON must be zero when changing the input channel multiplexor (ACS20). IREF Internal Reference Enable.
AT89LP3240/6440 21. Programmable Watchdog Timer The programmable Watchdog Timer (WDT) protects the system from incorrect execution by triggering a system reset when it times out after the software has failed to feed the timer prior to the timer overflow. By Default the WDT counts CPU clock cycles. The prescaler bits, PS0, PS1 and PS2 in SFR WDTCON are used to set the period of the Watchdog Timer from 16K to 2048K clock cycles.
21.1 Software Reset A Software Reset of the AT89LP3240/6440 is accomplished by writing the software reset sequence 5AH/A5H to the WDTRST SFR. The WDT does not need to be enabled to generate the software reset. A normal software reset will set the SWRST flag in WDTCON. However, if at any time an incorrect sequence is written to WDTRST (i.e. anything other than 1EH/E1H or 5AH/A5H), a software reset will immediately be generated and both the SWRST and WDTOVF flags will be set.
AT89LP3240/6440 22. Instruction Set Summary The AT89LP3240/6440 is fully binary compatible with the 8051 instruction set. The difference between the AT89LP3240/6440 and the standard 8051 is the number of cycles required to execute an instruction. Instructions in the AT89LP3240/6440 may take 1 to 9 clock cycles to complete. The execution times of most instructions may be computed using Table 22-1. Table 22-1.
Table 22-1.
AT89LP3240/6440 Table 22-1.
Table 22-1.
AT89LP3240/6440 22.1 Instruction Set Extensions The following instructions are extensions to the standard 8051 instruction set that provide enhanced capabilities not found in standard 8051 devices. All extended instructions start with an A5H escape code. For this reason random A5H reserved codes should not be placed in the instruction stream even though other devices may have treated these as NOPs. Other AT89LP devices may not support all of these instructions. 22.1.
22.1.3 CJNE A, @Ri, rel Function: Compare and Jump if Not Equal Description: CJNE compares the magnitudes of the Accumulator and indirect RAM location and branches if their values are not equal. The branch destination is computed by adding the signed relative-displacement in the last instruction byte to the PC, after incrementing the PC to the start of the next instruction.
AT89LP3240/6440 22.1.5 INC /DPTR Function: Increment Alternate Data Pointer Description: INC /DPTR increments the unselected 16-bit data pointer by 1. A 16-bit increment (modulo 216 ) is performed, and an overflow of the low-order byte of the data pointer from 0FFH to 00H increments the high-order byte. No flags are affected. Example: Registers DP1H and DP1L contain 12H and 0FEH, respectively, and DPS = 0.
22.1.7 LSL M Function: Shift MAC Accumulator Left Logically Description: The forty bits in the M register are shifted one bit to the left. Bit 0 is cleared. No flags are affected. Example: The M register holds the value 0C5B1A29384H. The following instruction, LSL M leaves the M register holding the value 8B63452708H. Bytes: 2 Cycles: 2 Encoding: A5 0 0 1 0 0 0 1 1 Operation: LSL (Mn+1) ←(Mn) n = 0 - 38 (M0) ← 0 22.1.
AT89LP3240/6440 22.1.9 MAC AB Function: Multiply and Accumulate Description: MAC AB multiplies the signed 16-bit integers in the register pairs {AX, A} and {BX, B} and adds the 32-bit product to the 40-bit M register. The low-order bytes of the 16-bit operands are stored in A and B, and the high-order bytes in AX and BX respectively. The four operand registers are unaffected by the operation.
22.1.11 MOVX A, @/DPTR Function: Move External using Alternate Data Pointer Description: The MOVX instruction transfesr data from external data memory to the Accumulator. The unselected Data Pointer generates a 16-bit address which targets EDATA, FDATA or XDATA. Example: DPS = 0, DPTR0 contains 0123H and DPTR1 contains 4567H. The following instruction sequence, MOVX MOVX A, @DPTR @/DPTR, A copies the data from address 0123H to 4567H.
AT89LP3240/6440 23. Register Index Table 23-1. Special Function Register Cross Reference Name Address Description Index ACC E0H ACSRA 97H Table 19-1 on page 130 ACSRB 9FH Table 19-2 on page 131 AREF AFH Table 19-3 on page 132 AUXR 8EH Table 3-4 on page 18 AX E1H Section 5.1 on page 24 B F0H BX F7H Section 5.
Table 23-1.
AT89LP3240/6440 Table 23-1. Special Function Register Cross Reference TH0 8CH Table 11-1 on page 51 TH1 8DH Table 11-1 on page 51 TH2 CDH Section 12.1 on page 61 TL0 8AH Table 11-1 on page 51 TL1 8BH Table 11-1 on page 51 TL2 CCH Section 12.
• P4.2/RST cannot be connected directly to VDD and any external capacitors connected to RST must be removed. • All external reset sources must be removed. • If P4.3 needs to be debugged in systems using the crystal oscillator, the external clock option should be selected. The quartz crystal and any capacitors on XTAL1 or XTAL2 must be removed and an external clock signal must be driven on XTAL1. Some emulator systems may provide a user-configurable clock for this purpose. Figure 24-1.
AT89LP3240/6440 • When using the Internal RC Oscillator during debug, DDA is located on the XTAL1/P4.0 pin. The P4.0 I/O function cannot be emulated in this mode. • When using the External Clock during debug, DDA is located on the XTAL2/P4.1 pin and the system clock drives XTAL1/P4.0. The P4.1 I/O and CLKOUT functions cannot be emulated in this mode. • When using the Crystal Oscillator during debug, DDA is located on the P4.3 pin and the crystal connects to XTAL1/P4.0 and XTAL2/P4.1. The P4.
Figure 25-1. In-System Programming Device Connections AT89LP3240/6440 Serial Clock P1.7/SCK Serial Out P1.6/MISO Serial In P1.5/MOSI SS VDD P1.4/SS RST P4.2/RST GND The Parallel interface is a special mode of the serial interface, i.e. the serial interface is used to enable the parallel interface. After enabling the interface serially over P1.7/SCK and P1.5/MOSI, P1.5 is reconfigured as an active-low output enable (OE) for data on Port 0.
AT89LP3240/6440 • The ISP interface uses the SPI clock mode 0 (CPOL = 0, CPHA = 0) exclusively with a maximum frequency of 5 MHz. • The AT89LP3240/6440 will enter programming mode only when its reset line (RST) is active (low). To simplify this operation, it is recommended that the target reset can be controlled by the In-System programmer. To avoid problems, the In-System programmer should be able to keep the entire target system reset for the duration of the programming cycle.
Figure 25-3. AT89LP6440 Memory Organization 00 3F Page Buffer User Fuse Row Page 0 Low User Signature Array Page 1 Low Page 0 Low Page 1 High Page 0 High Atmel Signature Array Page 0 Low Page 0 High Page 63 Low Page 63 High 3FFF Page 0 Low Page 0 High 1000 Page 511 Low Page 510 Low Page 511 High Page 510 High FFFF Page 1 Low Page 0 Low Page 1 High Page 1 High Data Memory Code Memory 00 25.
AT89LP3240/6440 For a summary of available commands, see Table 25-2 on page 162. Figure 25-4. Command Sequence Flow Chart Input Preamble 1 (AAh) Input Preamble 2 (55h) Input Opcode Input Address High Byte Input Address Low Byte Input/Output Data Address +1 Figure 25-5. ISP Command Packet (Serial) SS SCK MOSI MISO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Preamble 1 Preamble 2 Opcode Address High Address Low 7 6 5 4 3 2 1 0 Data In X X X X X 7 6 5 4 3 2 1 0 Data Out Figure 25-6.
Table 25-2. Programming Command Summary Command Opcode Addr High Addr Low Data 0 Data n Program Enable(1) 1010 1100 0101 0011 – – – Parallel Enable(2) 1010 1100 0011 0101 – – – Chip Erase 1000 1010 – – – – Read Status 0110 0000 xxxx xxxx xxxx xxxx Status Out Load Page Buffer(3) 0101 0001 xxxx xxxx 00bb bbbb Data In 0 ... Data In n Write Code Page(3) 0101 0000 aaaa aaaa asbb bbbb Data In 0 ...
AT89LP3240/6440 25.4 Status Register The current state of the memory may be accessed by reading the status register. The status register is shown in Table 25-3. Table 25-3. Status Register Bit – – – – LOAD SUCCESS WRTINH BUSY 7 6 5 4 3 2 1 0 Symbol Function LOAD Load flag. Cleared low by the load page buffer command and set high by the next memory write. This flag signals that the page buffer was previously loaded with data by the load page buffer command. SUCCESS Success flag.
25.7 User Configuration Fuses The AT89LP3240/6440 includes 11 user fuses for configuration of the device. Each fuse is accessed at a separate address in the User Fuse Row as listed in Table 25-5. Fuses are cleared by programming 00h to their locations. Programming FFh to a fuse location will cause that fuse to maintain its previous state. To set a fuse (set to FFh) the fuse row must be erased and then reprogrammed using the Fuse Write with Auto-erase command. The default state for all fuses is FFh.
AT89LP3240/6440 25.8 User Signature and Analog Configuration The User Signature Array contains 256 bytes of non-volatile memory in two 128-byte pages. The first page of the User Signature Array (0000H–007FH) is available for serial numbers, firmware revision information, date codes or other user parameters. The User Signature Array may only be written by an external device when the User Signature Programming Fuse is enabled. When the fuse is enabled, Chip Erase will also erase the first page of the array.
Figure 25-7. Serial Programming Power-up Sequence VDD tPWRUP RST tPOR + tSUT SS tZSS SCK 25.9.2 MISO HIGH Z MOSI HIGH Z Power-down Sequence Execute this sequence to power-down the device after programming. 1. Drive SCK low. 2. Wait at least tSSD and bring SS high. 3. Tristate MOSI. 4. Wait at least tSSZ and then tristate SS and SCK. 5. Wait no more than tPWRDN and power off VDD. Figure 25-8. Serial Programming Power-down Sequence VDD tPWRDN RST SS SCK 25.9.
AT89LP3240/6440 Figure 25-9. In-System Programming (ISP) Start Sequence tRLZ VDD XTAL1 RST tSTL SS tZSS tSSE SCK 25.9.4 MISO HIGH Z MOSI HIGH Z ISP Exit Sequence Execute this sequence to exit ISP mode and resume CPU execution mode. 1. Drive SCK low. 1. Wait at least tSSD and drive SS high. 2. Tristate MOSI. 3. Wait at least tSSZ and bring RST high. 4. Tristate SCK. 5. Wait tRHZ and tristate SS. Figure 25-10. In-System Programming (ISP) Exit Sequence VDD XTAL1 RST tSSZ SS SCK Note: 25.9.
CPHA = 0) where bits are sampled on the rising edge of SCK and output on the falling edge of SCK. For more detailed timing information see Figure 25-12. Figure 25-11. ISP Byte Sequence SCK MOSI 7 6 5 4 3 2 1 0 MISO 7 6 5 4 3 2 1 0 Data Sampled Figure 25-12. Serial Programming Interface Timing SS tSCK tSSE tSHSL SCK tSR tSSD tSF tSLSH tSOV tSOE tSOX tSOH MISO tSIS tSIH MOSI Figure 25-13.
AT89LP3240/6440 25.9.6 Timing Parameters The timing parameters for Figure 25-7, Figure 25-8, Figure 25-9, Figure 25-10, Figure 25-12 and Figure 25-13 are shown in Table . Table 25-7.
26. Electrical Characteristics 26.1 Absolute Maximum Ratings* Operating Temperature ................................... -40°C to +85°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground......-0.7V to +3.6V Maximum Operating Voltage ............................................ 3.6V DC Current per I/O Pin ..................................................
AT89LP3240/6440 26.3 26.3.1 Safe Operating Conditions Speed Figure 26-1 shows the safe operating frequencies for the AT89LP3240/6440 versus supply voltage. The device is only gauranteed to operate correctly within this area. Note that the on-chip Brown-out Detector (BOD) has a minimum threshold of 1.8V. Systems that rely on this BOD to prevent incorrect operation due to power loss should only operate at 12 MHz or below. Systems at higher frequencies may require an external BOD. Figure 26-1.
26.4.1 Supply Current (Internal Oscillator) Figure 26-3. Active Supply Current vs. VDD (8MHz Internal Oscillator) Active Supply Current vs. Vcc 8MHz Internal Oscillator Icc (mA) 6.5 85C 6.0 -40C 5.5 25C 5.0 4.5 4.0 3.5 2.4 2.7 3.0 3.3 3.6 Vcc (V) Figure 26-4. Idle Supply Current vs. VDD (8MHz Internal Oscillator) Idle Supply Current vs. Vcc 8MHz Internal Oscillator 2.00 85C -40C 1.75 Icc (mA) 25C 1.50 1.25 1.00 2.4 2.7 3.0 3.3 3.
AT89LP3240/6440 26.4.2 Supply Current (External Clock) Figure 26-5. Active Supply Current vs. Frequency Icc (mA) Active Supply Current vs. Frequency External Clock Source 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3.6V 3.3V 3.0V 2.7V 2.4V 0 5 10 15 20 25 Frequency (MHz) Figure 26-6. Idle Supply Current vs. Frequency Idle Supply Current vs. Frequency External Clock Source 5 3.6V 3.3V Icc (mA) 4 3.0V 3 2.7V 2 2.
26.4.3 Quasi-Bidirectional Input Figure 26-7. Quasi-bidirectional Input Transition Current at 3.3V ITL (μA) 0.0 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 85C -20 -40C -40 25C -60 -80 -100 -120 VIL (V) 26.4.4 Quasi-Bidirectional Output Figure 26-8. Quasi-Bidirectional Output I-V Source Characteristic at 3V 0.0 0 0.5 1.0 1.5 2.5 3.0 85C -40C -20 IOH (μA) 2.
AT89LP3240/6440 26.4.5 Push-Pull Output Figure 26-9. Push-Pull Output I-V Source Characteristic at 3V 2.4 0 2.5 2.6 2.7 2.8 2.9 3.0 85C -40C IOH1 (mA) -2 25C -4 -6 -8 -10 VOH1 (V) Figure 26-10. Push-Pull Output I-V Sink Characteristic at 3V 10 85C -40C IOL (mA) 8 25C 6 4 2 0 0.0 0.1 0.2 0.3 0.4 0.5 VOL (V) Note: 26.5 The IOL/VOL characteristic applies to Push-Pull, Quasi-Bidirectional and Open-Drain modes. Clock Characteristics Figure 26-11.
The values shown in these tables are valid for TA = -40°C to 85°C and VDD = 2.4 to 3.6V, unless otherwise noted. Table 26-1. Symbol External Clock Parameters Parameter (1) VDD = 2.4V to 3.6V VDD = 2.7V to 3.
AT89LP3240/6440 Figure 26-13. Typical Crystal Oscillator Swing with Quartz Crystal and C1=C2, TA = 25°C Vpp on XTAL1 (V) 4.0 3.6V 15pF 3.6V 10pF 3.5 3.6V 5pF 2.4V 15pF 3.0 2.4V 10pF 2.5 2.0 2.4V 5pF 4 8 12 16 20 Frequency (MHz) Note: 1. Replacing capacitor C1 with a resistor R1 of 4 MΩ results in similar swing levels on XTAL1. Figure 26-14. Typical Crystal Oscillator Swing with Ceramic Resonator and C1=C2, TA = 25°C Vpp on XTAL1 (V) 4.0 3.6V 15pF 3.5 3.6V 10pF 3.0 3.6V 5pF 2.5 2.
26.6 Reset Characteristics The values shown in this table are valid for TA = -40°C to 85°C and VDD = 2.4 to 3.6V, unless otherwise noted. Table 26-3. Reset Characteristics Symbol Parameter RRST Min Max Units Reset Pull-up Resistor 50 150 kΩ VPOR Power-On Reset Threshold 1.3 1.6 V VBOD Brown-Out Detector Threshold 1.8 2.0 V VBH Brown-Out Detector Hysteresis 200 300 mV tPOR Power-On Reset Delay 135 150 µs tWDTRST Watchdog Reset Pulse Width 26.
AT89LP3240/6440 3. Parameter tLHLL applies only when ALES = 1. 4. The strobe pulse width may be lengthened by 1, 2 or 3 additional tCLCL using wait states. 5. Parameter tWHLH applies only when ALES = 0, or when two MOVX instructions occur in succession. Figure 26-15. External Data Memory Read Cycle tLHLL ALE tLLDV tLLWL tWHLH tRLRH RD tRLAZ tAVLL PORT 0 tRLDV tLLAX tRHDX DATA IN A0 - A7 tAVWL tAVDV PORT 2 P2 tRHDZ tWHAX P2 A8 - A15 FROM DPH OR P2.0 - P2.7 Figure 26-16.
Table 26-5. SPI Master Characteristics Symbol Parameter tSIS Serial Input Setup Time 10 ns tSIH Serial Input Hold Time 10 ns tSOH Serial Output Hold Time 10 ns tSOV Serial Output Valid Time 35 ns Max Units Table 26-6. Min Max Units SPI Slave Characteristics Symbol Parameter Min tCLCL Oscillator Period 41.6 ns tSCK Serial Clock Cycle Time 4tCLCL ns tSHSL Clock High Time 1.5 tCLCL - 25 ns tSLSH Clock Low Time 1.
AT89LP3240/6440 Figure 26-18. SPI Slave Timing (CPHA = 0) SS tSR tSCK tSSE SCK (CPOL = 0) SCK (CPOL= 1) tSHSL tSLSH tSLSH tSHSL tSOV tSOE tSSD tSF tSOX tSOH MISO tSIS tSIH MOSI Figure 26-19. SPI Master Timing (CPHA = 1) SS tSCK SCK (CPOL = 0) SCK (CPOL = 1) tSF tSHSL tSLSH tSLSH tSHSL tSR tSIS tSIH MISO tSOV tSOH MOSI Figure 26-20.
26.9 Two-wire Serial Interface Characteristics Table 26-7 describes the requirements for devices connected to the Two-wire Serial Bus. The AT89LP3240/6440 Two-wire Serial Interface meets or exceeds these requirements under the noted conditions. The values shown in this table are valid for TA = -40°C to 85°C and VDD = 2.4 to 3.6V, unless otherwise noted. Timing symbols refer to Figure 26-21. Table 26-7.
AT89LP3240/6440 3. Cb = capacitance of one bus line in pF. 4. fCK = CPU clock frequency Figure 26-21. Two-wire Serial Bus Timing tHIGH tof tr tLOW tLOW SCL tSU;STA tHD;STA tHD;DAT tSU;DAT tSU;STO SDA tBUF 26.10 Serial Port Timing: Shift Register Mode The values in this table are valid for VDD = 2.4V to 3.6V and Load Capacitance = 80 pF.
26.11 Dual Analog Comparator Characteristics The values shown in this table are valid for TA = -40°C to 85°C and VDD = 2.4 to 3.6V, unless otherwise noted. Table 26-8. Dual Analog Comparator Characteristics Symbol Parameter Condition VCM Common Mode Input Voltage VOS Input Offset Voltage VAREF Analog Reference Voltage VΔREF Reference Delta Voltage tCMP Comparator Propagation Delay tAREF Reference Settling Time Min Max Units GND VDD V 20 mV 1.23 1.
AT89LP3240/6440 26.12 DADC Characteristics The values shown in these tables are valid for TA = -40°C to 85°C and VDD = 2.4 to 3.6V, unless otherwise noted. Table 26-9.
26.13 Test Conditions 26.13.1 AC Testing Input/Output Waveform Figure 26-24. AC Testing Input/Output Waveform(1) Note: 26.13.2 1. AC Inputs during testing are driven at VDD - 0.5V for a logic “1” and 0.45V for a logic “0”. Timing measurements are made at VIH min. for a logic “1” and VIL max. for a logic “0”. Float Waveform Figure 26-25. Float Waveform(1) Note: 26.13.3 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs.
AT89LP3240/6440 26.13.4 ICC Test Condition: Idle Mode Figure 26-27. Connection Diagram for ICC Idle Measurement. All Other Pins are Disconnected VDD VDD ICC RST XTAL2 (NC) CLOCK SIGNAL 26.13.5 VDD XTAL1 GND Clock Signal Waveform for ICC Tests Figure 26-28. Clock Signal Waveform for ICC in Active and Idle Modes, tCLCH = tCHCL = 5 ns VCC - 0.5V 0.45V 0.7 VCC tCHCX 0.2 VCC - 0.1V tCHCL tCLCH tCHCX tCLCL 26.13.6 ICC Test Condition: Power-down Mode Figure 26-29.
27. Ordering Information 27.1 Green Package Option (Pb/Halide-free) Code Flash 32KB 64KB Speed (MHz) 20 20 Power Supply Ordering Code Package AT89LP3240-20AU AT89LP3240-20PU 44A 40P6 AT89LP3240-20JU AT89LP3240-20MU 44J 44M1 AT89LP6440-20AU AT89LP6440-20PU 44A 40P6 AT89LP6440-20JU AT89LP6440-20MU 44J 44M1 Operation Range 2.4V to 3.6V Industrial (-40° C to 85° C) 2.4V to 3.6V Package Types 44A 44-lead, Thin Plastic Quad Flat Package (TQFP) 40P6 40-lead, 0.
AT89LP3240/6440 28. Packaging Information 28.1 44A – TQFP PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0˚~7˚ A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.
28.2 40P6 – PDIP D PIN 1 E1 A SEATING PLANE A1 L B B1 e E 0º ~ 15º C COMMON DIMENSIONS (Unit of Measure = mm) REF MIN NOM MAX A – – 4.826 A1 0.381 – – D 52.070 – 52.578 E 15.240 – 15.875 E1 13.462 – 13.970 B 0.356 – 0.559 B1 1.041 – 1.651 L 3.048 – 3.556 C 0.203 – 0.381 eB 15.494 – 17.526 SYMBOL eB Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion.
AT89LP3240/6440 28.3 44J – PLCC 1.14(0.045) X 45˚ PIN NO. 1 1.14(0.045) X 45˚ 0.318(0.0125) 0.191(0.0075) IDENTIFIER E1 D2/E2 B1 E B e A2 D1 A1 D A 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side.
28.4 44M1 – VQFN/MLF D Marked Pin# 1 ID E SEATING PLANE A1 TOP VIEW A3 A K L Pin #1 Corner D2 1 2 3 Option A SIDE VIEW Pin #1 Triangle E2 Option B K Option C b e Pin #1 Chamfer (C 0.30) Pin #1 Notch (0.20 R) BOTTOM VIEW COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 A3 0.20 REF b 0.18 0.23 0.30 D 6.90 7.00 7.10 D2 5.00 5.20 5.40 E 6.90 7.00 7.10 E2 5.00 5.20 5.40 e Note: JEDEC Standard MO-220, Fig.
AT89LP3240/6440 29. Revision History Revision No.
AT89LP3240/6440 3706C–MICRO–2/11
AT89LP3240/6440 Table of Contents Features ..................................................................................................... 1 1 2 3 Pin Configurations ................................................................................... 2 1.1 40P6: 40-lead PDIP ...........................................................................................2 1.2 44A: 44-lead TQFP (Top View) .........................................................................2 1.
Table of Contents (Continued) 8 9 7.4 Watchdog Reset ..............................................................................................36 7.5 Software Reset ................................................................................................36 Power Saving Modes ............................................................................. 36 8.1 Idle Mode .........................................................................................................36 8.
AT89LP3240/6440 Table of Contents (Continued) 16 Serial Interface (UART) .......................................................................... 85 16.1 Multiprocessor Communications .....................................................................85 16.2 Baud Rates ......................................................................................................87 16.3 More About Mode 0 .........................................................................................89 16.
Table of Contents (Continued) 22 Instruction Set Summary .................................................................... 143 22.1 Instruction Set Extensions .............................................................................147 23 Register Index ...................................................................................... 153 24 On-Chip Debug System ....................................................................... 155 24.1 Physical Interface .................................
AT89LP3240/6440 Table of Contents (Continued) 28 Packaging Information ........................................................................ 189 28.1 44A – TQFP ...................................................................................................189 28.2 40P6 – PDIP ..................................................................................................190 28.3 44J – PLCC ...................................................................................................
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: (+1) (408) 441-0311 Fax: (+1) (408) 487-2600 www.atmel.com 8051@atmel.com Atmel Asia Limited Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon HONG KONG Tel: (+852) 2245-6100 Fax: (+852) 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel: (+49) 89-31970-0 Fax: (+49) 89-3194621 Atmel Japan 9F, Tonetsu Shinkawa Bldg.
