User manual

RC200/203 Manual
www.celoxica.com Page 24
4.8.1 Programming the PLL via the parallel port or FPGA
The RC200 PLL chip can be soft programmed by either the FPGA or the parallel port. It
reverts to factory settings on a power on reset. The PLL chip supports a form of I
2
C.
If you are programming from the parallel port, the FPGA should be disabled by asserting
nPROG if there is any chance of it interfering with the programming of the PLL.

If you program any of the clocks apart from CLKUSER, you could stop the devices
from working, or damage them.
Programming the PLL from the parallel port
Three bits in the CPLD are used during PLL programming. The state of the data line can
be monitored at any time by reading bit 7 from address 3. The clock line for the data is
bit 6 of address 3. The bit for writing zeros is bit 7 of address 3. The data line is pulled u
by a resistor, so by writing 3[7]=1 a one will be written. When data is to be read from
p
the PLL chip, bit 7 of address 3 should be set to 1 so that the PLL chip can pull the data
ort
monitored by reading bit 7 from address 1 and the clock line for the data is bit 6 of
address 0. The data line is bit 7 of address 0.
cess to the FPGA. The device has a clock input of
formation about the device refer to the
RC200 data sheets (see page 35).
line to zero if required.
Programming the PLL from the FPGA
Programming the PLL from the FPGA is the same as programming from the parallel p
except that the registers are at a different address in the CPLD. The data line is
4.9 Ethernet
The RC200/203 is fitted with a Standard Microsystems Corporation LAN91C111 Ethernet
device. It supports 8-bit and 16-bit ac
25MHz, generated from the CPLD. For more in