User manual

RC200/203 Manual
www.celoxica.com Page 23
S1C1 nCS2 (not Chip Select) B10 D112
S1C2
R/nW (Read not
Write)
A10 C12
S1C4 -
S1C7
Not Byte Enable pins D6, C6, C4, C5 F8, E8, E6, E7
4.8 Clock generator (PLL)
The RC200/203 board has a Cypress CY22393 Programmable Clock Generator. The
generator is programmed to provide the following clocks:
Clock
generator
pin
Description RC200 FPGA
pin
RC203 FPGA
pin
GCLK2P
CLKUSER. Clock used to feed the
FPGA.
Y12 AB14
GCLK5P
24.576MHz clock. Used to feed
video input and audio chip.
B11 D13
GCLK6S
25.175MHz clock. Used to feed
VGA output (640 x 480 at 60Hz).
C11 E13
GCLK0P 27MHz video input clock. AB12 AD14
GCLK1P
50MHz crystal clock. This is used
to feed the CPLD.
E12 G14
GCLK7S Expansion clock 0 AA11 AC13
GCLK5S Expansion clock 1 W11 AA13
CLKCTRL V19 Y21
TV clock rates
The clock generator also produces 14.318MHz and 17.7MHz clocks for the RGB to
PAL/NTSC encoder. You can select between these values using the CLKCTRL signal (pin
15 on the clock generator).
FPGA clock: CLKUSER
CLKUSER has a default value of 133MHz. You can change the default value of CLKUSER
by programming the PLL from the FPGA or parallel port.