User manual

RC200/203 Manual
www.celoxica.com Page 21
A typical sequence of events for programming the SmartMedia from the parallel port
might be:
1. Check the SmartMedia device is fitted (address 3, bit 4).
2. Disable the FPGA from accessing the SmartMedia by asserting nPROG (address
3, bit 4).
3. Disable the SmartMedia state machine by asserting address 3, bit 3.
4. Wait for at least 1mS.
5. Assert nCS (address 3, bit 0).
6. Deassert ALE (address 3, bit 2).
7. Assert CLE (address 3, bit 1).
8. Write a SmartMedia command to CPLD address 2.
For example, refer to the SmartMedia Electrical Specification issued by the
SSFDC forum:
www.ssfdc.or.jp.
9. Deassert CLE.
10. Write a SmartMedia address.
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You need to carry out steps 1 to 4 for any access to the SmartMedia.
4.7 ZBT SRAM banks
, with
A. For more
information, please refer to the
RC200 data sheets (see page 35).
The RC200/203 is fitted with 2 ZBT RAM banks, capable of operating at up to 100MHz.
The RC200/203 Standard and Professional boards have two 2-MB banks fitted and the
RC200/203 Expert has two 4-MB banks. The RAM banks are IDT71T75702 devices
512K or 1024K 36-bit words. All lines are mapped directly to the FPG