User manual

RC200/203 Manual
www.celoxica.com Page 20
SmartMedia
pins
Signals CPLD pins
2 CLE 17
3 ALE 15
4 SMnWE 13
5 nWP 11
6 SMD0 10
7 SMD1 9
8 SMD2 7
9 SMD3 4
13 SMD4 2
14 SMD5 3
15 SMD6 6
16 SMD7 8
19 R/nB 12
20 SMnRD 14
21 SMnCS 16
4.6.2 FPGA access of SmartMedia
The RC200 SmartMedia is accessed by the FPGA via the CPLD.
A typical sequence of events might be:
1. Disable SmartMedia state machine by writing 1 on CPLD control address 0, bit
3.
2. Check the SmartMedia is fitted by reading the status of CPLD address 1, bit 4.
A value of 1 means that the SmartMedia has been successfully detected.
3. Assert nCS (CPLD address 0, bit 0).
4. Deassert ALE (CPLD address 0, bit 2).
5. Assert CLE (CPLD address 0, bit 1).
6. Write a command to address 2.
7. Deassert CLE.
8. Read or write to SmartMedia using address 2.
4.6.3 Parallel port access of SmartMedia
The RC200 SmartMedia is accessed from the parallel port via the CPLD.