User manual

RC200/203 Manual
www.celoxica.com Page 17
• Apply power to the board
• Press the Reset button on the board
• Insert the SmartMedia card whilst the board is switched on
4.4.5 Programming from a specific address in the SmartMedia:
1.
Address 3 for the upper byte (only the lower 5 bits of this byte
in the SmartMedia and
write t d wing steps:
• s the ID register of the code to find out if 4-word addresses are
•
hough the block checking the page
id page is skipped (if programming from address zero this is the
gramming, the FPGA is reset and the CPLD waits
C (Cyclical Redundancy Checking) which checks that the data stream is correct.
4.4.6 Reading data from the CPLD to the FPGA
To read e FPGA:
nd tristate the data bus.
0ns.
.
before reading data.
Set a block address in the CPLD using Address 4 for the lower byte of the
address and
are used).
2. Read from Address 5.
These steps will cause the CPLD to read from the relevant address
he ata to the FPGA. Data is written using follo
• CPLD sets up the FPGA for programming.
CPLD read
required.
CPLD reads the page valid byte (512+5) to see if it is valid.
If the page valid byte is invalid it searches t
valid byte until it finds a page that is valid.
The first val
CIS page).
• Data is copied to the FPGA until the FPGA is DONE. Bad pages are skipped.
The CPLD automatically adds 16 clock cycles after DONE to complete programming. If
the FPGA signals an error during pro
until a new SmartMedia is inserted.
It is assumed that if a single page is invalid then the entire block is invalid, and all the
pages within the block will have the block invalid byte set. The CPLD doesn't check the
SmartMedia ECC (Error Correcting Code) as the FPGA programming datastream has its
own CR
data from the RC200/203 CPLD and write it to th
1. Set up the address a
2. Wait at least 1
3. Set nCS low.
4. Wait at least 10ns
5. Set nRDWR low.
6. Wait at least 40ns