User manual

RC200/203 Manual

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Address value Description

Read and write (i.e. data pins) when FPGA is in parallel port

control mode

1 Read and write from host for SmartMedia

2 Not used

3 Read status of signals (8-bit data line from CPLD):

Bit 0: Master FPGA DONE signal

Bit 1: (not used; undefined)

Bit 2: FPGA nINIT signal

Bit 3: SmartMedia nBUSY signal

Bit 4: SmartMedia Detect (1 = SmartMedia inserted)

Bit 5: SmartMedia not Write Protect

Bit 6: SmartMedia state machine disable status

Bit 7: PLL data line (I

C bus)

Write status of signals:

Bit 0: SmartMedia nCS signal

Bit 1: SmartMedia CLE signal

Bit 2: SmartMedia ALE signal

Bit 3: Disable SmartMedia state machine

Bit 4: Master FPGA nPROG pin (inverted by CPLD)

Bit 5: Not used (Write 0)

Bit 6: PLL clock pin (I

C bus)

Bit 7: PLL data pin (I

C bus 1 = Tristate (input) 0=0)

4 Not used

5 Not used

6 Not used

7 CPLD version ID (0x51)

4.4 FPGA

The RC200 board has a Xilinx Virtex-II FPGA (part: XC2V1000-4FG456C on RC200 and

XC2V3000-4FG676 on RC203). The device has direct connections to the following

devices:

• CPLD

• ZBT RAM