User manual

RC200/203 Manual
www.celoxica.com Page 13
2 Data bus access of the SmartMedia
3
Upper byte of Block address for the SmartMedia (only the lower 5
bits are used)
4 Lower byte of Block address for the SmartMedia
5 Read from this address to start reprogramming of the FPGA from
SmartMedia
4.3.4 CPLD / parallel port interface
The RC200 CPLD supports an EPP (Enhanced Parallel Port) interface.
The parallel port is connected to the CPLD on the following pins:
CPLD pins Signal Parallel port pins
76 ParSCTL 13
77 ParPE 12
78 Parnwait 11
79 ParINIT 10
80 Pardata7 9
81 Pardata6 8
82 Pardata5 7
85 Pardata4 6
86 Pardata3 5
89 Paraddr 17
90 Pardata2 4
91 Parnreset 16
92 Pardata1 3
93 Parnerror 15
94 Pardata0 2
95 Parndata 14
96 Parnwrite 1
The CPLD has 3 address pins. When the CPLD is communicating with the parallel port
data lines, the 8 values within the 3-bit CPLD address are used as follows: