User manual

RC200/203 Manual

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4.3.2 CPLD clock

The RC200 CPLD has a clock input of 50MHz from a 50MHz crystal oscillator module. This

is divided by 2 to give an internal clock speed of 25MHz.

4.3.3 Register map in the CPLD for the FPGA

The RC200 CPLD has 3 address lines:

CPLD pins RC200 FPGA

pins

RC203 FPGA

pins

P5 Addr[0] AA19 AC21

P6 Addr[1] AB19 AD21

P7 Addr[2] R22 U24

Only the lower 5 of the 8 possible values within the 3-bit CPLD address are used by the

FPGA:

0 Control of SmartMedia and PLL

Bit 0: SmartMedia nCS signal

Bit 1: SmartMedia CLE signal

Bit 2: SmartMedia ALE signal

Bit 3: Disable SmartMedia state machine

Bit 4: Not used (Write 0)

Bit 5: Not used (Write 0)

Bit 6: PLL clock pin (I

C bus)

Bit 7: PLL data pin (I

C bus 1 = Tristate (input) 0=0)

1 Read status Register

Bit 0: Master FPGA DONE signal

Bit 1: (not used; undefined)

Bit 2: FPGA nINIT signal

Bit 3: SmartMedia nBUSY signal

Bit 4: SmartMedia Detect (1 = SmartMedia inserted)

Bit 5: SmartMedia not Write Protect

Bit 6: SmartMedia state machine disable status

Bit 7: PLL data line (I

C bus)