User manual

RC200/203 Manual
www.celoxica.com Page 11
4.3.1 Control and data pins
The RC200 CPLD has 10 control lines and 8 data lines. 3 of the control lines are used as
an address bus. The control lines have two meanings, depending on the
FPGA
operation mode
(see page 15). The FPGA operation mode is determined by whether the
CPLD pin P9 is set high or low.
CPLD
control line
RC200
FPGA
pin
RC203
FPGA
pin
Function (normal
FPGA operation)
Function (parallel
port control mode)
P0 Y19 AB21 CCLK Not used
P1 AA3 AC5
PnCS (Parallel Not
Chip Select) - Input
nWR (Not Write) -
Input
P2 Y4 AB6
nRDWR (Not Read
Write) – Input/Output
nRDWR (Not Read
Write) - Output
P3 A2 C4 nPROG Not used
P4 AB20 AD22 DONE Not used
P5 AA19 AC21 Address [0] – Output nINIT – Output
P6 AB19 AD21 Address [1] – Output nWAIT – Output
P7 R22 U24 Address [2] – Output nADDR – Input
P8 V22 Y24
nCS (Not Chip Select)
– Output
nDATA – Output
P9 T18 V20 Set high Set low
CPLD data line RC200 FPGA pin RC203 FPGA pin
FD0 V18 Y20
FD1 V17 VY19
FD2 W18 AA20
FD3 Y18 YAB20
FD4 Y5 AB7
FD5 W5 AA7
FD6 AB4 AD6
FD7 AA4 AC6