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Platform Developer’s Kit

RC200/203 Manual

Summary of content (90 pages)

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Platform Developer’s Kit RC200/203 Manual
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RC200/203 Manual Celoxica, the Celoxica logo and Handel-C are trademarks of Celoxica Limited. All other products or services mentioned herein may be trademarks of their respective owners. Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder. The product described in this document is subject to continuous development and improvement.
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RC200/203 Manual Contents 1 RC200/203 BOARD....................................................................... 4 2 RC200/203 OVERVIEW ................................................................... 5 3 INSTALLATION AND SET-UP ................................................................ 8 4 HARDWARE DESCRIPTION .................................................................. 9 5 RC200/203 PSL REFERENCE ......................................................... 38 6 INDEX ..............
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RC200/203 Manual Conventions A number of conventions are used in this document. These conventions are detailed below. Warning Message. These messages warn you that actions may damage your hardware. Handy Note. These messages draw your attention to crucial pieces of information. Hexadecimal numbers will appear throughout this document. The convention used is that of prefixing the number with '0x' in common with standard C syntax.
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RC200/203 Manual Assumptions & Omissions This manual assumes that you: • have used Handel-C or have the Handel-C Language Reference Manual • are familiar with common programming terms (e.g. functions) • are familiar with MS Windows This manual does not include: • instruction in VHDL or Verilog • instruction in the use of place and route tools • tutorial example programs. These are provided in the Handel-C User Manual www.celoxica.
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RC200/203 Manual 1 RC200/203 board The RC200 and RC203 are platforms for evaluation and development of highperformance FPGA-based applications. The platforms include a Xilinx Virtex-II FPGA, external memory, programmable clocks, Ethernet, Audio, Video, SmartMedia, Parallel port, RS-232 and PS/2 keyboard and mouse. Supporting software includes PAL, DSM, the RC200 PSL, and the FTU2 File Transfer Utility.
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RC200/203 Manual 2 RC200/203 overview The devices and connectors on the board are shown in the overview of devices (see page 9) and overview of connectors (see page 10). Note: the Xilinx Virtex II device on the RC203 has part number XC2V3000-FG676. 2.1 Standard kit • Virtex-II 2V1000-4 (RC200) or 2V3000-4 (RC203) FPGA • Ethernet MAC/PHY with 10/100baseT socket • 2 banks of ZBT SRAM providing a total of 4-MB www.celoxica.
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RC200/203 Manual • Video support including: • • Composite video in/out • S-Video in/out • VGA out • Camera in (Camera socket provides camera power) AC'97 compatible Audio including • • Microphone in • Line in (Stereo) • Line/Headphone out (Stereo) Connector for SmartMedia Flash memory for storage of BIT files • CPLD for configuration/reconfiguration and SmartMedia management • • Power-on load from SmartMedia • Load when SmartMedia installed • Reconfigure on demand from FPGA Parallel port connector
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RC200/203 Manual • 16-MB SmartMedia card • Colour camera 2.3 Expert kit This provides the following features in addition to the Professional Kit: • Bluetooth wireless module • Memory banks expanded to 4-MB each giving a board total of 8-MB • TFT flat panel display or touch screen 2.
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RC200/203 Manual 3 Installation and set-up Unpacking the board You should take care to avoid static discharge when handling the RC200/203 board, as this may damage it. You are recommended to use an earth strap. If an earth strap is not available, ensure that you make contact with earth before and during handling of the board, and only handle the board by its edges. Connecting the cables The board must be powered down before you attach cables.
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RC200/203 Manual 4 Hardware description This section describes the devices on the RC200, how to program the FPGA and how to transfer data between the host, SmartMedia and FPGA. Schematics for the board are available in InstallDir\PDK\Documentation\PSL\RC200\RC200VBDOC.pdf for the RC200 or in InstallDir\PDK\Documentation\PSL\RC203\RC203VBDOC.pdf for the RC203 (for installations using PDK3.1 or later).
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RC200/203 Manual 4.2 RC200/203 connectors CONNECTORS ON THE RC200/203 4.3 CPLD The RC200/203 has a Xilinx XC95144XL 3.3V CPLD. The CPLD is connected to the: • FPGA • Parallel port • SmartMedia Flash RAM • JTAG chain The CPLD can configure the FPGA with data received from SmartMedia memory, or via the parallel port. www.celoxica.
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RC200/203 Manual 4.3.1 Control and data pins The RC200 CPLD has 10 control lines and 8 data lines. 3 of the control lines are used as an address bus. The control lines have two meanings, depending on the FPGA operation mode (see page 15). The FPGA operation mode is determined by whether the CPLD pin P9 is set high or low.
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RC200/203 Manual 4.3.2 CPLD clock The RC200 CPLD has a clock input of 50MHz from a 50MHz crystal oscillator module. This is divided by 2 to give an internal clock speed of 25MHz. 4.3.
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RC200/203 Manual 2 Data bus access of the SmartMedia 3 Upper byte of Block address for the SmartMedia (only the lower 5 bits are used) 4 Lower byte of Block address for the SmartMedia 5 Read from this address to start reprogramming of the FPGA from SmartMedia 4.3.4 CPLD / parallel port interface The RC200 CPLD supports an EPP (Enhanced Parallel Port) interface.
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RC200/203 Manual Address value Description 0 Read and write (i.e.
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RC200/203 Manual • Ethernet • Clock generator • Video input • Video DAC • RGB to PAL/NTSC encoder • Audio codec • RS-232 • PS/2 connectors • Expansion header • 2 seven-segment displays • 2 blue LEDs • 2 contact switches • Bluetooth (if fitted) • TFT Flat screen (if fitted) • Touchscreen (if fitted) Details of pin connections are given in the sections about these devices.
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RC200/203 Manual 4.4.2 Programming the FPGA using the FTU2 program Celoxica provides a File Transfer Utility program, FTU2, which simplifies the process of programming the RC200 FPGA via the parallel port. 4.4.3 Programming the FPGA from the parallel port To program the RC200 Virtex-II from the parallel port: 1. Check that the board is connected and powered by reading the CPLD version ID (CPLD address value 7). The board may not return the ID if the FPGA is controlling the parallel port.
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RC200/203 Manual • Apply power to the board • Press the Reset button on the board • Insert the SmartMedia card whilst the board is switched on 4.4.5 Programming from a specific address in the SmartMedia: 1. Set a block address in the CPLD using Address 4 for the lower byte of the address and Address 3 for the upper byte (only the lower 5 bits of this byte are used). 2. Read from Address 5.
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RC200/203 Manual 7. Tristate nRDWR. 8. Set nCS high. 4.4.7 Writing data to the CPLD from the FPGA To write from the RC200 FPGA to the CPLD: 1. Set up the address and data bus if not already tristated. 2. Wait at least 10ns. 3. Set nCS low. 4. Wait at least 10ns. 5. Set nRDWR high and enable the data bus. 6. Wait at least 40ns. 7. Tristate nRDWR. 8. Set nCS high. 9. Tristate the data bus. 4.4.
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RC200/203 Manual 4.4.9 Using the FPGA in parallel port control mode When the CPLD control line P9 is set low the RC200 FPGA has direct control over the parallel port. The nRDWR signal (CPLD control line P2) defines the direction of the databus. 4.5 Parallel port The RC200/203 has an IEEE 1284-compatible parallel port. You can use the parallel port to: • program the FPGA (see page 16) • program the SmartMedia card (see page 20) • read data from and write data to the FPGA (see page 18) 4.
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RC200/203 Manual SmartMedia pins Signals CPLD pins 2 CLE 17 3 ALE 15 4 SMnWE 13 5 nWP 11 6 SMD0 10 7 SMD1 9 8 SMD2 7 9 SMD3 4 13 SMD4 2 14 SMD5 3 15 SMD6 6 16 SMD7 8 19 R/nB 12 20 SMnRD 14 21 SMnCS 16 4.6.2 FPGA access of SmartMedia The RC200 SmartMedia is accessed by the FPGA via the CPLD. A typical sequence of events might be: 1. Disable SmartMedia state machine by writing 1 on CPLD control address 0, bit 3. 2.
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RC200/203 Manual A typical sequence of events for programming the SmartMedia from the parallel port might be: 1. Check the SmartMedia device is fitted (address 3, bit 4). 2. Disable the FPGA from accessing the SmartMedia by asserting nPROG (address 3, bit 4). 3. Disable the SmartMedia state machine by asserting address 3, bit 3. 4. Wait for at least 1mS. 5. Assert nCS (address 3, bit 0). 6. Deassert ALE (address 3, bit 2). 7. Assert CLE (address 3, bit 1). 8. Write a SmartMedia command to CPLD address 2.
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RC200/203 Manual Pins connecting RAM Bank 0 to the FPGA SSRAM pin Function Rc200 FPGA pins (in ascending order) RC203 FPGA pins (in ascending order) S0D0 S0D35 Data [35:0] K20, L19, L20, K18, L18, E18, F18, G18, H18, J18, J17, K17, B12, A13, B13, A14, B14, B15, A16, B16, A17, B17, B18, A19, B19, C12, D12, C13, D13, C14, D14, C15, D15, C16, D16, C17 M22, N21, N22, M20, N20, G20, H20, J20, K20, L20, L19, M19, D14, C15, D15, C16, D16, D17, C18, D18, C19, D19, D20, C21, D21, E14, F14, E15, F15, E16, F16
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RC200/203 Manual S1C1 nCS2 (not Chip Select) B10 D112 S1C2 R/nW (Read not Write) A10 C12 S1C4 S1C7 Not Byte Enable pins D6, C6, C4, C5 F8, E8, E6, E7 4.8 Clock generator (PLL) The RC200/203 board has a Cypress CY22393 Programmable Clock Generator. The generator is programmed to provide the following clocks: Clock generator pin Description RC200 FPGA pin RC203 FPGA pin GCLK2P CLKUSER. Clock used to feed the FPGA. Y12 AB14 GCLK5P 24.576MHz clock. Used to feed video input and audio chip.
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RC200/203 Manual 4.8.1 Programming the PLL via the parallel port or FPGA The RC200 PLL chip can be soft programmed by either the FPGA or the parallel port. It reverts to factory settings on a power on reset. The PLL chip supports a form of I2C. If you are programming from the parallel port, the FPGA should be disabled by asserting nPROG if there is any chance of it interfering with the programming of the PLL.
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RC200/203 Manual Ethernet pins Function RC200 FPGA pins (in ascending order) RC203 FPGA pins (in ascending order) ED0 - ED15 Data [15:0] M21, N22, N21, P22, P21, R21, T22, T21, U22, U21, V21, W22, W21, Y22, Y21, M17 P23, R24, R23, T24, T23, U23, V24, V23, W24, W23, Y23, AA24, AA23, AB24, AB23, P19 EC0 - EC2 Address [2:0] M18, M20, M19 P20, P22, P21 EC3 and EC4 Not byte enable N20, N19 R22, R21 EC5 Not Read P20 T22 EC6 Not Write P19 T21 EC7 Interrupt R20 U22 EC8 Asynchronous rea
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RC200/203 Manual Video input pins Function RC200 FPGA Pins (in RC203 FPGA Pins (in ascending order) ascending order) VIND0 – VIND7 Data pins [7:0] AA20, AA18, AA17, AB17, AA16, AB16, AA15, AA14 AC22, AC20, AC19, AD19, AC18, AD18, AC17, AC16 VINC0 RTS1 W20 AA22 VINC1 RTS0 N17 R19 VINC2 RTCO P17 T19 VINC3 SCL N18 R20 VINC4 SDA P18 T20 VINC5 CEP R18 U20 4.
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RC200/203 Manual For more information on this device, please refer to the RC200 data sheets (see page 35).
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RC200/203 Manual 4.11.3 TFT flat panel display An Optrex T-51382D064J-FW-P-AA thin film transistor (TFT) flat panel display is provided as an optional feature with the RC200/203 Expert board. It is connected directly to the FPGA. TFT control pins Function RC200 FPGA pins RC203 FPGA pins LCD0 Clock pin AA12 AC14 LCD1 Hsync pin W17 AA19 LCD2 Vsync pin Y17 AB19 LCD3 Data enable pin W16 AA18 The TFT has 18 data pins: RGB4 - RGB9, RGB14 - RGB19 and RGB24 - RGB29.
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RC200/203 Manual Description Function Rc200 FPGA pins RC203 FPGA pins Serial0 CTS (Clear To Send) T19 V21 Serial1 RxD (Receive data) U20 W22 Serial2 RTS (Ready To Send) U19 W21 Serial3 TxD (Transmit data) V20 Y22 4.14 Mouse and keyboard PS/2 ports The RC200/203 board has two PS/2 ports, labelled Mouse and Keyboard on the PCB. These are 6-pin mini DIN sockets that will accept any standard PS/2 mouse or keyboard.
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RC200/203 Manual 7-segment pins Display segment RC200 FPGA pins RC203FPGA pins A1 a G3 J5 B1 b H4 K6 C1 c L3 N5 D1 d L4 N6 E1 e K3 M5 F1 f F3 H5 G1 g G4 J6 DP1 decimal place L5 N7 Display 1 (display on right-hand side) 7-segment pins Display segment RC200 FPGA pins RC203FPGA pins A2 a J4 L6 B2 b J3 L5 C2 c H5 K7 D2 d F5 H7 E2 e L6 N8 F2 f H3 K5 G2 g G5 J7 DP2 decimal place K4 M6 4.
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RC200/203 Manual Expansion header pins ATA function Expansion header function RC200 RC203 FPGA pins FPGA pins 1 Reset IO0 R2 U4 2 GND GND - - 3 D7 IO2 M2 P4 4 D8 IO1 M1 P3 5 D6 IO4 N2 R4 6 D9 IO3 N1 R3 7 D5 IO6 P2 T4 8 D10 IO5 P1 T3 9 D4 IO8 M4 P6 10 D11 IO7 M3 P5 11 D2 IO10 N4 R6 12 D12 IO9 N3 R5 13 D2 IO12 P3 T5 14 D13 IO11 P4 T6 15 D1 IO14 R4 U6 16 D14 IO13 R3 U5 17 D0 IO16 T3 V5 18 D15 IO15 T2 V4 19 GND G
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RC200/203 Manual Expansion header pins ATA function Expansion header function RC200 RC203 FPGA pins FPGA pins 34 nPDIAG IO26 U3 W5 35 DA0 IO27 N6 R8 36 DA2 IO28 P6 T8 37 nCS0 IO29 M5 P7 38 nCS1 IO30 V2 Y4 39 nDASP1 IO31 R1 U3 40 GND GND - - 41 Pin removed Pin removed - - 42 Pin removed Pin removed - - 43 IO32 IO32 V1 Y3 44 +3.3v +3.3v (0.5Amps max) - - 45 IO33 IO33 N5 R7 46 +5v +5v (0.
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RC200/203 Manual There are also two LEDs indicating when power is on for the board (LED D2) and when the FPGA has been programmed (LED D1). These are located to the left of the Celoxica copyright mark on the board. They are controlled by the CPLD and you cannot program them from the FPGA. 4.18 Contact switches There are two buttons in the lower left corner of the board (Button 0 and Button 1). When pressed, these act as momentary high inputs into the FPGA.
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RC200/203 Manual Pin JTAG Function 1 TMS 2 - 3 TDI 4 TDO 5 - 6 TCK 7 VCC (+3.3V) 8 GND 9 VCC (+3.3V) Some of the RC200/203 devices are connected into a JTAG chain. The chain is as follows: The order of the devices in the JTAG chain is: CPLD (0), FPGA (1), Video Decoder chip (2). The instruction register (IR) length for these devices is 5, 5, 3 respectively. 4.
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RC200/203 Manual 4.22 Bluetooth module A Mitsumi WML-C09 Bluetooth module is provided on the RC200/203 Expert board. It is connected directly to the FPGA. Bluetooth pins Function RC200 FPGA pins RC203 FPGA pins BT0 RX pin W13 AA15 BT1 TX pin Y13 AB15 BT2 RTS pin W12 AA14 BT3 CTS pin V12 Y14 BT4 Reset pin U12 W14 4.23 Touch screen A Fujitsu Components N010-0554-T042 6.4 inch touch screen is provided as an optional feature with the RC200/203 Expert board.
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RC200/203 Manual Device Information Xilinx XC95144XL CPLD Click on the XC9500XL link at: http://www.xilinx.com/xlnx/xweb/xil_publications_ind ex.jsp then choose the XC95144XL PDF Xilinx Virtex-II FPGA part: XC2V10004FG456C IEEE 1284 Parallel Port specification Click on the Virtex-II link at: http://www.xilinx.com/xlnx/xweb/xil_publications_ind ex.jsp http://www.fapo.com/ieee1284.htm SmartMedia http://www.ssfdc.or.jp/english/ IDT IDT71T75702 ZBT RAM http://www.idt.com/docs/71T75702_DS_59004.
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RC200/203 Manual Device Information Fujitsu Components N010-0554-T042 touch screen http://www.fceu.fujitsu.com/pdf/Datasheet_4Wire_To uchPanels.pdf Burr Brown Products TSC2200 Touch Screen controller http://www-s.ti.com/sc/ds/tsc2200.pdf www.celoxica.
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RC200/203 Manual 5 RC200/203 PSL reference The RC200/203 Platform Support Library is provided as part of the Platform Developer's Kit. Throughout this documentation "RC200" should be taken to refer to both RC200 and RC203 unless explicitly noted otherwise. This Library targets both RC200 and RC203 boards although there are four slightly different versions: • rc200.hcl targets the Standard and Professional versions of the RC200 • rc200e.hcl targets the Expert version of the RC200. • rc203.
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RC200/203 Manual 5.2 Clock definitions To set the clock, you need to define one of the 4 preprocessor macros listed below, before including rc200.hch in your source code. If none of these are defined, no clock is set. • RC200_CLOCK_USER • RC200_CLOCK_EXPCLK0 • RC200_CLOCK_EXPCLK1 • RC200_TARGET_CLOCK_RATE You can check the actual clock rate of your design using RC200_ACTUAL_CLOCK_RATE. 5.2.
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RC200/203 Manual a DCM will be used in frequency synthesis mode to generate the nearest approximation to the desired frequency (from a base of 50MHz). Note that the performance of generated clocks, in terms of parameters like jitter, may be worse than native clock frequencies. For more details about the DCM, consult the Xilinx Data Book. Below 24MHz, Handel-C clock dividers will be used to divide the frequency down (since this is the lower bound of the DCM clock synthesis). This is handled transparently.
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RC200/203 Manual Parameters: Index: LED index, of type unsigned 1. Value: Boolean control value, of type unsigned 1. Timing: 1 clock cycle. Description: Turns the Index number LED either on or off. A Value of 1 means ON, and 0 means OFF. 5.4.2 RC200LED*Write() macros extern macro proc RC200LED0Write (Value); extern macro proc RC200LED1Write (Value); Parameters: Value: Boolean control value, of type unsigned 1 Timing: 1 clock cycle Description: Controls LED 0 or LED1.
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RC200/203 Manual Parameters: Index: Button index, of type unsigned 1. Return value: Boolean button state, of type unsigned 1. Description: Reads a value from either of the push buttons. A value of 1 means ON (or closed), a value of 0 means OFF (or open). 5.5.2 RC200Button*Read() macros extern macro expr RC200Button0Read (); extern macro expr RC200Button1Read (); Parameters: None. Return value: Boolean button state, of type unsigned 1. Description: Reads a value from push button 0 or 1. 5.5.
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RC200/203 Manual Parameters: Shape: Bitmask control value, of type unsigned 8. Timing: 1 clock cycle. Description: Sets a particular shape in the seven-segment display. Shape is a binary mask where 1 means ON and 0 means OFF. Each of the eight bits corresponds to a segment of the display (7-segments for the digit and one for the decimal point). The segments are numbered as shown below. The rightmost bit in Shape targets segment a, and the left-most bit targets the decimal point (dp).
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RC200/203 Manual 5.7 ZBT SRAM macros If you want to read data from or write data to RAM you need to: 1. Call RC200PL1RAM0Run() or RC200PL1RAM1Run(), depending on which RAM bank you want to target. You need to call this in parallel with the rest of your RAM code. 2. Set the address for the read or write using one of the RC200PL1RAMXSetReadAddress or RC200PL1RAMXSetWriteAddress() macros. 3. Call one of the RC200PL1RAM*Read() or RC200PL1RAM*Write() macros.
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RC200/203 Manual Parameters: Address: Address of data to read/write on the next clock cycle, of type unsigned 19 on the Standard and Professional versions of the RC200, and unsigned 20 on Expert boards. Timing: 1 clock cycle. Description: Sets the address of data for the Read or Write which will occur on the next cycle. seq { RC200PL1RAM0SetReadAddress (Addr); RC200PL1RAM0Read (&Data); } Example: 5.7.
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RC200/203 Manual 5.7.5 Writing data to RAM extern macro proc RC200PL1RAM0Write (Data); extern macro proc RC200PL1RAM1Write (Data); Parameters: Data: Data value of type unsigned 36. Timing: 1 clock cycle. Description: Writes a single item of data to the address specified by the call to RC200PL1RAM*SetWriteAddress() on the previous clock cycle. 5.8 PS/2 port macros To write data to or read data from the mouse or keyboard, you need to: 1. Call RC200PS2MouseRun() or RC200PS2KeyboardRun(). 2.
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RC200/203 Manual Parameters: DataPtr: Pointer to an lvalue of type unsigned 8. Timing: 1 or more clock cycles (the read is blocked until data is ready). Description: Reads a single item of data from the mouse PS/2 port and stores it in the lvalue pointed at by DataPtr. Note that these are raw bytes from the mouse. To do interpreted access (e.g. mouse positions) you should use the PAL PS/2 API. 5.8.
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RC200/203 Manual Parameters: DataPtr: Pointer to an lvalue of type unsigned 8. Timing: 1 or more clock cycles (the read is blocked until data is ready). Description: Reads a single item of data from the keyboard PS/2 port and stores it in the lvalue pointed at by DataPtr. Note that these are raw bytes from the keyboard. To do interpreted access (e.g. ASCII keyboard characters) you should use the PAL PS/2 API. 5.8.
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RC200/203 Manual Parameters: BaudRate: A code selecting the initial baud. Use the baud codes set by RC200RS232SetBaudRate(). Parity: A code selecting the initial parity. Use the parity codes set by RC200RS232SetParity(). FlowControl: A code selecting the initial flow control. Use the flow codes set by RC200RS232SetFlowControl(). ClockRate: Clock rate of the clock domain of the call to this macro, in Hz. Timing: Does not terminate in normal use.
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RC200/203 Manual Baud code Baud selected (number of transitions per second) RC200RS232_75Baud 75 RC200RS232_110Baud 100 RC200RS232_300Baud 300 RC200RS232_1200Baud 1200 RC200RS232_2400Baud 2400 RC200RS232_9600Baud 9600 RC200RS232_19200Baud 19200 RC200RS232_38400Baud 38400 RC200RS232_57600Baud 57600 RC200RS232_115200Baud 115200 RC200RS232_230400Baud 230400 RC200RS232_460800Baud 460800 RC200RS232_921600Baud 921600 Selecting the parity extern macro proc RC200RS232SetParity (Parity);
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RC200/203 Manual Parameters: FlowControl: A code selecting the flow control. Possible values: RC200RS232FlowControlNone RC200RS232FlowControlSoft RC200RS232FlowControlHard These correspond to the following settings: No flow control; Software flow control (XON/XOFF); Hardware flow (RTS/CTS) Timing: 1 clock cycle. Description: Changes the flow control of the RS-232 interface. 5.9.
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RC200/203 Manual 5.10.1 Touch screen management tasks extern macro proc RC200TouchScreenRun (ClockRate); Parameters: ClockRate: Clock rate of the clock domain of the call to this macro, in Hz. Timing: Does not terminate in normal use. Description: Runs the device management tasks for the touch screen. You must run this macro in parallel with accesses to the device. 5.10.
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RC200/203 Manual Parameters: XPtr: Pointer to an lvalue of type unsigned 10. YPtr: Pointer to an lvalue of type unsigned 9. TouchPtr: Pointer to an lvalue of type unsigned 1. Timing: 1 clock cycle. Description: Returns the last sensed position of the pointing device on the touch screen, scaled to 640 x 480 resolution (the same as the LCD screen underneath). Note that the calibration of this scaling is only approximate; for precision use, each should be individually calibrated.
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RC200/203 Manual Parameters: Mode: Video mode expression, see below. ClockRate: Clock rate of the clock domain of the call to this macro, in Hz. Timing: Does not terminate in normal use. Description: Drives the video output in the selected mode. You must run this macro in parallel with accesses to the device. Mode must be one of the expressions listed below. The VGA modes drive the VGA connector with VESA GTF compatible timings. The horizontal resolution will adapt according to ClockRate.
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RC200/203 Manual 1024 x 768 @ 76Hz 85.000000 MHz 1152 x 864 @ 72Hz 100.000000 MHz 1280 x 1024 @ 75Hz 140.000000 MHz 720 x 576i @ 50Hz 13.846154 MHz 720 x 480i @ 60Hz 13.846154 MHz 5.11.2 Enabling video output extern macro proc RC200VideoOutEnable (); Parameters: None. Timing: Typically 1 clock cycle. Description: Enables the video output. You need to call this macro before you call RC200VideoOutWrite24() or RC200VideoOutWrite30(). 5.11.
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RC200/203 Manual Parameters: Mode: A video mode expression. ClockRate: Clock rate of the clock domain of the call to RC200VideoOutRun() in Hz. Used to determine the horizontal screen resolution. Description: Macro expressions which return the dimensions of the visible screen (from 0 to RC200VideoOutGetVisibleXY()1), and the total number of rows and columns scanned in including blanking. "CT" variants require a compile time constant mode, i.e.
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RC200/203 Manual 5.11.6 Current scan position extern macro expr RC200VideoOutGetX (); extern macro expr RC200VideoOutGetY (); Parameters: None. Description: Macro expressions that return the current scan position of the screen output. A call to RC200VideoOutWrite24() or RC200VideoOutWrite30() will write a colour to the position on screen returned by these methods. 5.11.
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RC200/203 Manual • RC200VideoInReadPixelPairRGB() reads a pair of RGB pixels. • RC200VideoInReadPixelRGB() reads a single RGB pixel. Before you use one of these macros you need to: 1. Call RC200VideoInRun() in parallel with the rest of the video input code. 2. Select the type of video input using RC200VideoInSetInput(). If you do not set the input, Composite (CVBS) input will be used as a default 3. Select the colour–encoding standard using RC200VideoInSetStandard().
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RC200/203 Manual Parameters: Standard: A code selecting the TV colour-encoding standard. Possible values RC200VideoInStandardPALNTSC or RC200VideoInStandardSECAM The first code selects PAL or NTSC and the second selects SECAM. The default value is RC200VideoInStandardPALNTSC. Timing: 1 or more clock cycles. Description: Selects which colour-encoding standard to expect at the selected input. You need to call RC200VideoInSetInput() before using this macro.
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RC200/203 Manual 5.12.5 Reading a pair of RGB pixels extern macro proc RC200VideoInReadPixelPairRGB (XPtr, YPtr, LeftRGBPtr, RightRGBPtr); Parameters: XPtr: Pointer to an lvalue of type unsigned 9. YPtr: Pointer to an lvalue of type unsigned 9. LeftRGBPtr: Pointer to an lvalue of type unsigned 24. RightRGBPtr: Pointer to an lvalue of type unsigned 24.
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RC200/203 Manual Parameters: XPtr: Pointer to an lvalue of type unsigned 9. YPtr: Pointer to an lvalue of type unsigned 9. RGBPtr: Pointer to an lvalue of type unsigned 24. Timing: 1 or more clock cycles (read blocks until data is ready). Description: Reads a single RGB encoded pixel from the video input selected by RC200VideoInSetInput(). This form of input requires a colour space converter which is built automatically.
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RC200/203 Manual 5.13.2 Setting the audio input extern macro proc RC200AudioInSetInput (Input); Parameters: Input: Either RC200AudioInLineIn or RC200AudioInMicrophone. Timing: 1 or more clock cycles. Description: Sets the input of the audio ADC to be either the line in connector or the microphone. 5.13.3 Boosting the input amplifier RC200AudioInSetMicrophoneBoost (Boost); Parameters: Boost: Data value of type unsigned 2. Timing: 1 or more clock cycles.
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RC200/203 Manual Parameters: SampleRateCode: A code selecting the sampling rate. Possible values: Sample rate code Sample rate (Hz) RC200AudioSampleRate8000 8000 RC200AudioSampleRate11025 11025 RC200AudioSampleRate16000 16000 RC200AudioSampleRate22050 22050 RC200AudioSampleRate32000 32000 RC200AudioSampleRate44100 RC200AudioSampleRate48000 44100 48000 (default) Timing: 1 clock cycle. Description: Changes the sample rate of the audio input. 5.13.
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RC200/203 Manual 5.13.8 Setting the output sample rate extern macro proc RC200AudioOutSetSampleRate (SampleRateCode); Parameters: SampleRateCode: a code selecting the sampling rate. Possible values: Sample rate code Sample rate (Hz) RC200AudioSampleRate8000 8000 RC200AudioSampleRate11025 11025 RC200AudioSampleRate16000 16000 RC200AudioSampleRate22050 22050 RC200AudioSampleRate32000 32000 RC200AudioSampleRate44100 44100 RC200AudioSampleRate48000 48000 (default) Timing: 1 clock cycle.
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RC200/203 Manual 5.14.1 Bluetooth management tasks extern macro proc RC200BluetoothRun (ClockRate); Parameters: ClockRate: Clock rate of the clock domain of the call to this macro, in Hz. Timing: Does not terminate in normal use. Runs the device management tasks for the Bluetooth interface. You must run this macro in parallel with accesses to the device. Description: 5.14.2 Resetting the Bluetooth device extern macro proc RC200BluetoothReset (); Parameters: None. Timing: 1 or more clock cycles.
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RC200/203 Manual Parameters: Data: Data value of type unsigned 8. Timing: 1 or more clock cycles (blocks until data is sent). Description: Writes a single item of data to the Bluetooth interface from the expression Data. Note that these are raw bytes to the Bluetooth interface device. By default the Bluetooth interface device uses the BlueCore Serial Protocol (BCSP) from Cambridge Silicon Radio. 5.15 SmartMedia macros The RC200 supports SmartMedia devices between 4 and 128 megabytes.
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RC200/203 Manual To perform a read or write using logical addressing you need to: 1. Call RC200SmartMediaCheckLogicalFormat(). If this macro returns 1 to indicate failure you need to perform a logical format on the card using the Celoxica FTU2 program. 2. Set the address, using RC200SmartMediaSetLogicalAddress(). 3. Call RC200SmartMediaRead() or RC200SmartMediaWrite() for each byte of data. For the last byte of data, set the LastData compile-time constant to 1. 4.
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RC200/203 Manual 5.15.3 Initializing the SmartMedia device extern macro proc RC200SmartMediaInit (ResultPtr); Parameters: ResultPtr: Pointer to register of type unsigned 1. Returns 0 for success, 1 for failure. Timing: 240 clock cycles or more. Description: Initializes the SmartMedia device and controller. You must call this macro when the board is switched on, or when a SmartMedia card is inserted. It performs a reset of the device and reads the ID to identify the size of the card.
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RC200/203 Manual 5.15.6 Erasing SmartMedia memory extern macro proc RC200SmartMediaErase (Address, ResultPtr); Parameters: Address: Block address in bytes of type unsigned 27. ResultPtr: Pointer to register of type unsigned 1. Returns 0 for success, 1 for failure. Timing 250 clock cycles or more. Description: Performs an erase on the entire block set by Address. Note that for 16 pages per block (4/8MB cards) the block address resides in the top 18 bits.
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RC200/203 Manual The logical formatting operation creates a logical address map on the third valid block in the card. This is to allow for corrupt blocks near the start of the card; the CIS/IDI fields are on the first valid block.
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RC200/203 Manual Parameters: ResultPtr: Pointer to register of type unsigned 1. Returns 0 if the card is correctly formatted with the Celoxica logical address map, or 1 if it is not. Timing: 350 clock cycles or more. Description: This macro checks to see if the SmartMedia card is formatted according to the Celoxica logical address map. If it is, it returns 0 and stores the number of the block where the logical map is stored.
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RC200/203 Manual Parameters: WriteNotRead: Compile time constant. To select a write, use 1. To select a read, use 0. Address: Address in bytes, of type unsigned 27. Timing: 170 cycles or more. Description: Sets the address for a SmartMedia read or write operation, using logical addressing. The only valid commands to follow this macro are RC200SmartMediaRead() or RC200SmartMediaWrite(). Ensure that that no other CPLD actions are carried out once an address has been set.
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RC200/203 Manual Parameters: DataPtr: Register to store the data to be read, of type unsigned 8. LastData: Compile time constant to indicate the end of the data. Set LastData to 1 to indicate that the last byte of data is being read. Timing: 160 clock cycles or more (including setting the address). Description: Reads sequential data, one byte at a time, from the SmartMedia device. You need to call RC200SmartMediaSetAddress() before you call this macro for the first time.
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RC200/203 Manual A write process erases the entire contents of the block, even if you only write one byte. Completing a read or write operation extern macro proc RC200SmartMediaOperationEnd (ResultPtr); Parameters: ResultPtr: Pointer to register of type unsigned 1. Returns 0 for success, 1 for failure. Timing: 1 or more clock cycles. It will take more than one clock cycle if you call the macro directly after the last call to RC200SmartMediaRead() or RC200SmartMediaWrite().
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RC200/203 Manual 5. Once the whole packet has been read or written, call RC200EthernetReadEnd() or RC200EthernetWriteEnd(). Important considerations: • You must call RC200EthernetReadEnd() or RC200EthernetWriteEnd() at the end of a read or write, and the driver will not reposnd correctly to further commands until this is done.
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RC200/203 Manual Parameters: Mode: Specifies initialization settings for Ethernet interface. This should be set using one of the pre-defined modes. The only mode currently available is RC200EthernetModeDefault: RC200EthernetEnable (RC200EthernetModeDefault); Timing: 1400 clock cycles or more. Blocks if the Ethernet device is not ready. Description: Takes the Ethernet device out of isolation mode, and programs the transmit and receive parameters according to Mode.
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RC200/203 Manual Parameters: None. Timing: Dependant on clock rate. Minimum: 4 clock cycles. Description: Sets the reset pin low for at least 100ns, forcing the Ethernet chip to reset. You need to call RC200EthernetEnable() after you reset the device. 5.16.6 Reading a packet Starting the read process extern macro proc RC200EthernetReadBegin (StatusPtr, DestinationPtr, SourcePtr, DataByteCountPtr, ResultPtr); Parameters: StatusPtr: Pointer to data of type unsigned 16.
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RC200/203 Manual Parameters: DataPtr: Pointer to data of type unsigned 8. Returns a byte of data from the received packet. ResultPtr: Pointer to data of type unsigned 1. Returns 1 (failure) or 0 (success). Timing: 2 or 7 clock cycles alternately, and up to 12 clock cycles for the final read. The macro reads a byte at a time, but Ethernet accesses are 16-bit. When a byte of data is already buffered on the chip the read only takes 2 clock cycles.
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RC200/203 Manual 5.16.7 Writing a packet to the network Starting the write process extern macro proc RC200EthernetWriteBegin (Destination, DataByteCount, ResultPtr); Parameters: Destination: Data of type unsigned 48. Specifies the destination MAC address for the packet. DataByteCount: Data of type unsigned 11. Specifies the number of data bytes to be sent. Possible values: 64-1518. ResultPtr: Pointer to data of type unsigned 1. Returns 1 (failure) or 0 (success). Timing: At least 100 clock cycles.
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RC200/203 Manual Parameters: Data: Data of type unsigned 8, containing a byte of data to write to the packet. ResultPtr: Pointer to data of type unsigned 1. Returns 1 (failure) or 0 (success). Timing: 1 or 6 clock cycles alternately. This is because the macro writes a byte at a time, but Ethernet accesses are 16-bit. When a byte of data is already buffered on the chip the write only takes 1 clock cycle. Timing may differ if other accesses to the chip precede a write operation.
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RC200/203 Manual Parameters: ImageAddress: Data of type unsigned 16, specifying the block address to start accessing the SmartMedia card at for reconfiguration. Timing: If reconfiguration is success, the macro does not return. Description: This macro reconfigures the FPGA from the SmartMedia. You must run it in parallel with RC200CPLDRun(), and after calling RC200CPLDEnable().
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RC200/203 Manual Parameters: None. Timing: 2 cycles if CPLD is ready for use, otherwise, undetermined. Description: You need to call this macro in parallel with RC200CPLDRun(), and before accesses to the CPLD. The macro waits until the CPLD is ready and then sets the CPLD internal mode to normal operation. Refer to the RC200 Hardware and Installation Manual for more details. par { RC200CPLDRun(); seq { RC200CPLDEnable(); // code for CPLD accesses ... } } Example: 5.
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RC200/203 Manual Parameters: None. Timing: 1 clock cycle. Description: Enables the Send Protocol driver. You cannot use this at the same time as the RC200 SmartMedia macros. You need to call RC200CPLDRun() and RC200CPLDEnable() before calling this macro. You must call this macro before any calls to RC200SendProtocolWrite() or RC200SendProtocolRead(). 5.19.2 Disabling the Send Protocol driver extern macro proc RC200SendProtocolDisable(); Parameters: None. Timing: 1 clock cycle.
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RC200/203 Manual Parameters: DataPtr: Pointer to data of type unsigned 8, to return data read from the host PC. Timing: Variable. Depends on whether host PC has sent data to read. Description: Reads one byte of data from the host PC and writes it to the FPGA. This macro will block if the host has not sent any data to be read. You must call RC200SendProtocolEnable() before using this macro. 5.
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RC200/203 Manual 6 Index A audio........................................28, 61 audio clock 23 boosting input 62 gain level 62 hardware description 28 input source 62 output volume 63 reading from 61, 63 sample rate 62, 64 writing to 61, 64 reading from 65 resetting 65 writing to 65 enabling 75 mode 76 reading from 77 resetting 76 writing to 79 Expert RC200 ................................. 38 F FPGA .......................................
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RC200/203 Manual parallel port control mode 15, 19 RC200AudioRun .............................. 61 reading from FPGA 18 RC200BluetoothRead ....................... 65 writing to FPGA 18 RC200BluetoothReset ...................... 65 Professional RC200............................6 RC200BluetoothRun......................... 65 PS/2 ports.................................29, 46 RC200BluetoothWrite....................... 65 R RC200BoardIsExpert........................ 40 RAM .......................
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RC200/203 Manual RC200RS232Read ........................... 51 RC200VideoOutGetVBlank ................ 57 RC200RS232Run............................. 48 RC200VideoOutGetVisible* macros .... 55 RC200RS232SetBaudRate ................ 49 RC200VideoOutGetVSync ................. 57 RC200RS232SetFlowControl ............. 50 RC200VideoOutRun ......................... 53 RC200RS232SetParity...................... 50 RC200VideoOutWrite24 .................... 56 RC200RS232Write ...........................
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RC200/203 Manual erasing 66, 69 formatting 71 FPGA access 20 initializing 66, 68 pages per block 69 parallel port access 20 reading from 72 resetting 68 setting an address writing to 71, 72 73 Standard RC200................................5 T touch screen................................... 51 pointer position 52 V video input ..................................... 57 camera 58 clock 23 colour-encoding standard 58 composite 58 RGB 60 S-video 58 YCrCb 59 video output ........