User manual

Tutorial: Handel-C advanced optimization
Try modifying the code in the version2 project in the TutorialEstimator workspace to use this pipeline,
rebuild it, and open the estimation summary again. You will see that the longest path is unchanged, and
there has been no significant change in the number of LUTs or other logic elements used, despite
calculating the values for
C and D in two separate places. This is because the optimizations in DK include
identifying common expressions which do not execute at the same time, and sharing hardware between
them. The details on the new longest paths when using the pipeline are shown below:
LONGEST PATHS AFTER MODIFYING THE VERSION2 PROJECT
8.4 Reducing the logic area
The section on Reducing the logic delay (see page 90) looked at using the Logic Estimator to help
increase the maximum clock rate at which a design could run. This section looks at how you can use the
Estimator to reduce the logic area of a design.
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