User manual

Tutorial: Handel-C advanced optimization
It should appear as below:
ESTIMATION SUMMARY FROM VERSION1 PROJECT
The first section of the summary provides an estimation of the logic area, described in terms of LUTs,
FFs, memory bits and miscellaneous other components. The numbers of these components are listed
per source file in the project, with a total at the end. Clicking on the link to the source file will take you to
a page providing more detail on how the logic area is distributed within the source file.
The second section of the summary provides an estimate of the logic and routing delay for the project,
giving times for the specified target device and speed grade. Note that the estimate given here is
different from that in DK2, which did not include routing delay, so the delays will appear to be longer,
though they are in fact more accurate. The exact delay can only be found by implementing the design
using the FPGA vendors Place and Route tools. Clicking on the link to
Detailed path information takes you
to a page showing which lines of Handel-C source code contributed to the longest path in the design.
Note that if the Technology Mapper is not turned on, the information provided will not be as detailed or
accurate as that shown here.
The following sections include instructions for reducing the logic delay and area of the design in the
version1 project in the TutorialEstimator workspace.
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