User manual

Tutorial: Handel-C advanced optimization
8 Tutorial: Using the logic estimator
The following examples illustrate the use of the DK Logic Estimator to produce smaller and faster
designs. A basic knowledge of Handel-C is assumed and some knowledge of digital electronics and
design techniques will also be helpful.
The tutorial workspace can be opened by selecting
Start>Programs>Celoxica>Platform Developer's
Kit>Tutorials>TutorialEstimator.
New users are recommended to work through the following topics in order:
•
Enabling the logic estimator (see page 87)
•
Using the logic estimator results (see page 88)
•
Reducing the logic delay (see page 90)
•
Reducing the logic area (see page 93)
8.1 Enabling the logic estimator
The logic estimator is a tool included in DK which generates a HTML-based report on the expected logic
area and delay of the Handel-C code in the current project. This information can be very useful to
increase the speed and reduce the size of a Handel-C design. Further information on the detailed
operation of the logic estimator can be found in the DK online help.
To enable the logic estimator for a given project, select the
Project>Settings menu, and select the Linker
tab. Make sure that the Settings for drop-down list is set to EDIF. Check the box for Generate estimation info.
Also make sure that the box for
Enable technology mapper on the Synthesis tab is checked.
ENABLING THE LOGIC ESTIMATOR
Enabling the technology mapper allows the logic estimator to produce more accurate results. If the
mapper is not enabled, logic estimation can still be used but the timing and resource usage information
will be expressed in general terms, rather than specific components and delays.
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