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Tutorial: Handel-C code optimization
7 Tutorial: Handel-C advanced optimization
The following examples illustrate advanced methods of optimizing Handel-C code to produce smaller
and faster designs. This builds on the content of the Code Optimization Tutorial, which should be studied
first. Two main techniques are covered; pipelining and client-server architectures. A thorough
knowledge of Handel-C is assumed, and some knowledge of digital electronics and design techniques
will also be helpful.
•
Pipelining (see page 78)
•
Pipelines and replicators (see page 79)
•
Client-Server architecture (see page 80)
7.1 Pipelining
A simple technique for increasing the clock rate of a Handel-C design is to split complex operations over
several cycles. However, this results in more cycles being required to perform the operation. Pipelining
splits operations up in the same way, but achieves the same data throughput as the original circuit.
The following code illustrates a complex expression that is might result in a low clock rate for the design
it is included in:
while (1)
{
a = (b + c) * (d + e);
}
This can be split into two operations to calculate the sums, which can be executed in parallel, and then
the following cycle the multiplication can be performed. This will result in each line having a shallower
logic depth, allowing a higher clock rate.
while (1)
{
par
{
sum1 = (b + c);
sum2 = (d + e);
}
a = sum1 + sum2;
}
However, the original operation took only one cycle, and the modified version takes 2 cycles. If all three
lines of code are executed in parallel, a two stage pipeline will be formed, as shown below:
while (1)
{
par
{
/* pipeline stage 1 */
sum1 = (b + c);
sum2 = (d + e);
/* pipeline stage 2 */
a = sum1 + sum2;
}
}
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