User manual

Tutorial: Handel-C and VGA graphics output
6 Tutorial: Handel-C code optimization
The following examples illustrate different methods of optimizing Handel-C code to produce smaller and
faster designs. A basic knowledge of Handel-C is assumed, and some knowledge of digital electronics
and design techniques will also be helpful.
Timing and area efficient code (see page 71)
Loops and control code (see page 74)
6.1 Timing and area efficient code
A common goal in digital hardware design is to produce circuits which are small and run at a high clock
rate. As Handel-C is a higher level language than HDLs, a new user may sometimes be unclear as to
how to produce optimal designs. The following sections illustrate a Handel-C coding style which will
usually result in area efficient and fast designs.
•
Complex statements (see page 71)
•
Arrays and memories (see page 72)
•
Macro procedures versus functions (see page 74)
•
Static initialization (see page 74)
6.1.1 Complex statements
When DK compiles Handel-C code for hardware implementation, it generates all the logic required to
execute each line of code in a single clock cycle. Therefore, the more complex a line of code is, the
longer it will take to execute, and the lower the design clock rate will be. Some of the operators which
produce complex hardware are division, multiplication, addition/subtraction and shifting by a variable.
The complexity also depends on width of the operands – larger variables need more hardware. The
example code below shows a mixture of simple and complex statements:
unsigned 16 a, b, c, d;
a = b + c;
a = d + c;
a = d >> 2;
a = ((b << c) + (b * d);
The first three lines of code are quite simple, but the fourth is very complex. The clock rate of the whole
design will be limited by the fourth line, so it would be better to break it up into several simpler
statements:
unsigned 16 temp1, temp2;
par
{
temp1 = b << c;
temp2 = b * d;
}
a = temp1 + temp2;
Although the modified code will take two cycles to execute it will be better overall as the whole design will
now be able to run at a higher clock rate. In many designs it is possible to use
pipelining to hide this extra
cycle. The use of pipelining is explained in the Advanced Optimization tutorial.
A further issue with complex statements is the use of signals. The code below shows the complex
statement from the previous example implemented using signals:
www.celoxica.com
Page 71