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HANDEL-C RAM READ
The timing for a write operation given in the data sheet corresponds to this diagram:
RAM WRITE OPERATION
The address and data must be stable when the write enable is active. Handel-C has a synchronous
timing model and there is no facility for designing asynchronous systems. You can only guarantee that
the value of a changing expression is stable at the end of a clock cycle (at the rising edge of the clock).
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