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You can capture this equation in a Handel-C macro expression and use it to evaluate the required
number of clock cycles at compile time.
/* Return the number of clock cycles needed for a time delay.
* Parameter: Time : compile time constant in units of nanoseconds
* Requires an externally defined variable ClockFrequency which
* holds the system clock frequency in units of megahertz
*/
macro expr Time2Cycles (Time) = ((Time*ClockFrequency)+500)/1000;
The device operation for a read is shown in the following macro procedure:
macro proc RAMRead (Address, DataPtr)
{
seq (i = 0; i != Time2Cycles (35); i++)
{
par
{
RAMAddress = Address;
(*DataPtr) = RAMData.In;
nRAMOE = 0;
}
}
}
The variable
RAMAddress is a signal and so the value of Address appears on the FPGA/PLD pins no
longer than 5ns after the start of the clock cycle in which the macro is executed. The register pointed to
by
DataPtr latches the value of RAMData. In at the rising edge of the clock after the macro completes.
The macro takes a number clock cycles whose time duration is greater than or equal to 35ns. Here is a
timing diagram for the macro execution:
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