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DSM tutorials
in this example. The DK online help contains more information about timing constraints. To locate this
information select the Index tab from the online help navigation window and enter
timing as a keyword.
Here are interface and output expression definitions for the RAM device:
static signal unsigned 16 RAMAddress;
static signal unsigned 8 RAMDataOut;
static signal unsigned 1 RAMDataOE = 0;
static signal unsigned 1 nRAMOE = 1;
static signal unsigned 1 nRAMWE = 1;
interface bus_out ( )
RAMAddr (unsigned 16 RAMAddress = RAMAddress)
with {data = RAMAddrBus, outtime=5};
interface bus_ts (unsigned 8 In)
RAMData (unsigned 8 RAMData = RAMDataOut,
unsigned 1 oe = RAMDataOE)
with {data= RAMDataBus, outtime=5, intime=5};
interface bus_out ( )
RAMOE (unsigned 1 nRAMEnable = nRAMOE)
with {data = RAMOEPin, outtime=5};
interface bus_out( )
RAMCS(unsigned 1 nRAMChipSelect = 0)
with {RAMCSPin};
interface bus_out( )
RAMWE(unsigned 1 nRAMWriteEnable = nRAMWE)
with {data = RAMWEPin, outtime=5};
The timing for a read operation given in the data sheet corresponds to this timing diagram:
RAM READ OPERATION
The data becomes valid 25ns after the address is presented on the address pins and the output enable
pin is set low. Maximum input and output routing delays of 5ns specified by the timing constraints add
10ns to the total access time. You need a macro procedure that sets the value of the address and output
enable expressions and then samples the data input at least 35ns later.
In Handel-C the only unit of time is the clock cycle, you must calculate how many clock cycles are
needed to delay for 35ns using the system clock frequency. Time delay, clock frequency and clock
cycles are related by this equation:
clock cycles = time * clock frequency
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