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Here are macro expressions for the RAM pins:
static macro expr RAMAddrBus =
{"A1", "A2","A3", "A4", "A5", "A6", "A7", "A8",
"A9","A10","A11","A12","A13","A14","A15","A16"};
static macro expr RAMDataBus =
{"D1","D2","D3", "D4","D5","D6","D7","D8"};
static macro expr RAMCSPin = {"CS"};
static macro expr RAMWEPin = {"WE"};
static macro expr RAMOEPin = {"OE"};
The Cypress CY7C1049B-25 has an access time of 25ns, which corresponds to a maximum clock
frequency of 40MHz. When you include routing delays to the access time the maximum clock frequency
may be reduced further.
If your target clock frequency is less than or comparable with the speed of the RAM, you should use the
built-in Handel-C RAM support to define a RAM like this:
ram unsigned 8 Ram0[65536] with {
offchip = 1,
addr = RAMAddrBus,
data = RAMDataBus,
cs = RAMCSPin,
we = RAMWEPin,
oe = RAMOEPin,
westart = 2,
welength = 1
};
This RAM definition requires a divided Handel-C clock. You can find a more information about the built in
RAM support in the DK online help. This is located under the contents at:
DK Help>Handel-C Language
Reference Manual
>Interfacing to other logic or devices>Use of RAMs and ROMs with Handel-C.
Now you can implement the RAM driver using Handel-C array syntax as shown in the following code:
macro proc RAMRead (Address, DataPtr)
{
(*DataPtr) = Ram0[Address];
}
macro proc RAMWrite (Address, Data)
{
Ram0[Address] = Data;
}
If you require the system to clock faster than the RAM, use interfaces instead of the RAM definition to
connect to your external RAM device and implement macro procedures to control the expressions on
the interfaces.
First define the interfaces and interface output expressions to connect to the RAM device pins. Most
often a variable is used as the expression on an output interface however constants (macro expressions
and expressions formed from infix operators such as
a+b, or !a) are also syntactically correct. This
example uses a constant to set the RAM chip select always on. The interfaces require timing constraints
which inform the FPGA/PLD place and route or fitter tools how much routing delay can be tolerated
between the expression on the interface and the pin on the FPGA/PLD package. You must select
appropriate values for your design. Very small constraints can prevent the place and route or fitter
software from successfully processing your design. Input and output timing constraints of 5ns are used
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