User manual

Tutorial: Using the logic estimator
9.9 Improving performance with retiming
The previous version of the FIR (Using Retiming) used retiming but did not change the design at all.
Build the
Retiming1 project in the TutorialFIR workspace, accessible from Start>Programs>Celoxica>Platform
Developer's Kit>Tutorials>TutorialFIR on the Start Menu. Open the logic estimator summary - Summary.html
in the folder
PDK/Tutorials/General/TutorialFIR/retiming1/EDIF, and click on the Detailed path information link.
This will take you to the page show below, where clicking on the links in the left pane will jump the right
pane to the location of code with the highest logic delay, as shown below.
LONGEST PATH SUMMARY FOR RETIMING1 PROJECT
From this estimation, you can see that the longest path is still in the multiplier. The retimer will be able to
reduce the longest path further still if it has more registers to spread through components such as the
multiplier. You can modify the design to give the retimer more registers to work with by adding a shift
register immediately before the output of the FIR filter. This will increase the latency, but will allow a
significantly higher clock rate. The modified code is shown below:
#define RETIME_REGS 3
...
RetimeRegs[0] = RecurseAdd(MultResults, NumberMults-1);
par(i=1; i<RETIME_REGS; i++)
{
RetimeRegs[i] = RetimeRegs[i-1];
}
FirPtr->Output = RetimeRegs[RETIME_REGS-1];
By using a
#define for the number of extra registers to add at the FIR output, you can easily adjust it to
achieve different clock rates. With no extra registers, the
Retiming1 project achieved 120MHz. (Retiming1
project is in the TutorialFIR workspace, accessible from Start>Programs>Celoxica>Platform Developer's
Kit
>Tutorials>TutorialFIR on the Start Menu). The Retiming2 in the TutorialFIR workspace, accessible from
Start>Programs>Celoxica>Platform Developer's Kit>Tutorials>TutorialFIR on the Start Menu, contains the
modified code for retiming with extra registers.
Try building the project with different clock rates and number of extra registers. You will find that the FIR
code in the
Retiming2 project can achieve 130MHz with 1 extra register, 139MHz with 2, 150Mhz with 3,
152MHz with 4 and 153MHz with 6. These clock rates should be compared to a rate of 120MHz with no
extra registers. Note that registers can not be added indefinitely to achieve higher clock rates, as there
will be a certain minimum amount of logic in any design which can not be broken down any further.
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