User manual

Tutorial: Using the logic estimator
RETIMER OUTPUT DURING BUILD
In this you can see that the retimer has found a path with a delay of 27.31ns - which is equivalent to the
final delay in the estimation summary above for the
Version4 project. The retimer has discovered a
requirement for a delay of 8.333ns, and has tried to meet this, achieving 8.878ns. Although this is longer
than the required delay, it is likely to be close enough for the PAR tools to achieve the requested clock
rate.
After the build is complete, open the logic estimator summary -
Summary.html in the folder
PDK/Tutorials/General/TutorialFIR/retiming1/EDIF. The summary from the logic estimator is shown below:
LOGIC ESTIMATION SUMMARY FOR RETIMING1 PROJECT
You can see that the the estimated delay is much lower than that of the Version4 project, and is also lower
than that of the version using ALU mapping and a pipelined adder tree (Using a pipelined adder tree).
The retiming has achieved higher performance than the embedded multipliers used in ALU mapping
because it has been able to move registers inside the FIR to balance the logic in each pipeline stage. In
this case, this has resulted in distributed multipliers which are faster then the embedded multipliers.
The PAR is run as a post-build step in DK for all the FIR projects, so you can compare the clock rate
actually achieved. For the
Version4 project the FIR ran at 65MHz, when using ALU mapping with a
pipelined adder tree (
alumapping2 project), it ran at 90MHz, and with this retiming project, it can run at
120MHz.
The next version of the FIR example will increase performance further still by better use of the retiming.
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