User manual

Tutorial: Using the logic estimator
The longest path is now through the multiplier again, but as this is now an embedded ALU, it is not
possible to break it down and gain any further increase in speed.
The next step in the tutorial will look at an alternative approach: using
retiming to increase the speed of
the FIR filter.
9.8 Using Retiming
For this stage in the tutorial, we will return to the source code as used in "Reducing logic area". This
version uses the
RecurseAdd macro, rather than the pipelined adder tree. You can see the source
code in the
Retiming1 project in the TutorialFIR workspace, accessible from
Start>Programs>Celoxica>Platform Developer's Kit>Tutorials>TutorialFIR on the Start Menu.
Note that ALU mapping has been turned off, as it could limit the ability of the retimer to improve the
performance of the design.
With retiming off, as in "Reducing logic area", the logic estimator gave the following results:
LOGIC ESTIMATION SUMMARY FOR VERSION4 PROJECT
In this case, the DK logic estimator turned out to be too pessimistic, and the Xilinx Place And Route
(PAR) tools actually achieved a delay of 15.128ns. This happens because the logic estimator is using an
approximation to the routing delay, while the PAR tools have a fully placed and routed design to use in
determining the timing. In any case, the actual performance is always above the estimation from DK.
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