User manual

Tutorial: Using the logic estimator
LONGEST PATH SUMMARY FOR ALUMAPPING1 PROJECT
Our goal is now to reduce the delay on this path further. We will do this by pipelining the adder tree which
is currently built by the
RecurseAdd macro. This macro is explained in detail in the Using parallel
multipliers
(see page 107) section of this tutorial, but an example of the adder tree it is building is shown
below (only for 8 inputs):
result
7 6 5 4 3 2 1 0
ADDER TREE BUILT BY RECURSEADD MACRO
The long logic path is because several layers of additions must be completed within a single clock cycle.
We will re-write the adder tree to be pipelined, using a layer of registers after each layer of additions.
This will increase the latency, but the throughput will remain the same, at one new result per clock cycle.
The adder tree will then appear as below:
result
7 6 5 4 3 2 1 0
reg reg
reg reg reg reg
PIPELINED ADDER TREE
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