User manual

Tutorial: Using the logic estimator
Compared to the summary for the previous project (Reducing logic area), it can be seen that the number
of LUTs and "other" (e.g. fast carry chains) components has dropped significantly, while 11 ALUs are
now used, and there has been an increase in the number of FFs. It can also be seen that with the use of
the embedded ALUs, the estimated longest path has been reduced by almost 30%. If you click on
detailed path information, you can see where the critical path is now, as shown below:
LONGEST PATH SUMMARY FOR ALUMAPPING1 PROJECT
With the use of ALU mapping, the longest path is now through the RecurseAdd macro, which adds the
results of the multiplications. The next version of the FIR tutorial (Using a pipelined adder tree) will
address this, decreasing the longest path further still.
9.7 Using a pipelined adder tree
In the previous version of the FIR tutorial (Using ALU Mapping), the use of ALU mapping reduced the
logic delay of the multipliers in the FIR to the point where the longest path was no longer there, but was
in the RecurseAdd macro instead. The longest paths from the previous version are shown again below:
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