User manual

Tutorial: Using the logic estimator
In the summary from the Logic Estimator below, the hardware usage can be seen to be significantly
reduced from the previous version (Single cycle FIR), with the number of FFs down by 6%, LUTs down
by 34% and other components down by 38%. This summary can be viewed by building the project for
EDIF, and opening
Summary.html in the folder PDK/Tutorials/General/TutorialFIR/Version4/EDIF.
LOGIC ESTIMATION SUMMARY FOR VERSION4 PROJECT
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