User manual

Tutorial: Using the logic estimator
LOGIC ESTIMATION SUMMARY FOR VERSION3 PROJECT
9.5 Reducing logic area
There is one final optimization which we will make to the FIR filter to reduce the area it takes up on a
device.
It is possible to reduce the number of multipliers in the FIR filter by up to 50%, by taking advantage of the
fact the FIR filters can have symmetrical coefficients. For example, a FIR filter with 7 taps may have
coefficients:
{1, 2, 3, 4, 3, 2, 1}
The design of FIR filter used in the previous version (Using parallel multipliers (see page 107)) would
have the structure shown below:
z
-1
z
-1
z
-1
z
-1
z
-1
z
-1
Σ
h(0) h(1) h(2) h(3) h(4) h(5) h(6)
y(n)
x(n)
STANDARD FIR
An FIR filter which takes advantage of the symmetrical coefficients will add the input data in pairs before
doing the multiplications, as shown below:
z
-1
z
-1
z
-1
z
-1
z
-1
z
-1
+ + +
Σ
h(0) h(1) h(2) h(3)
x(n)
y(n)
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