User manual

Tutorial: Using the logic estimator
the adder tree. Note that the logic area in the Estimator Summary is larger for the Version2 and Version3
projects than for Version1 (Initial version), which is to be expected as we now have a larger number of
multipliers and adders. The tradeoff is that the number of clock cycles taken to process each data
sample is significantly reduced.
9.4 Single cycle FIR
The previous version of the FIR (Using parallel multipliers) modified the code to allow the multiplication
by coefficients and the summing of these results each to be performed in a single clock cycle. It is now
therefore possible to make the whole FIR take a single cycle by executing all the parts of it in parallel
rather than in sequence.
Several changes are required to make the FIR single cycle. The first is to put a
par{} block inside the
while(1) loop in the FirFilter macro proc. The next change is needed to handle the incoming data,
as the filter must now be able to accept a new item every cycle. The code was originally as shown below:
do
{
TempData = FirPtr->Input;
}while (FirPtr->InputValid == 0);
par
{
DataArray[Taps - 1] = TempData;
par (i = Taps - 1; i != 0; i--)
{
DataArray[i-1] = DataArray[i];
}
FirPtr->InputValid = 0;
}
This must be changed to:
DataArray[Taps - 1] = FirPtr->Input;
par (i = Taps - 1; i != 0; i--)
{
DataArray[i-1] = DataArray[i];
}
This imposes the requirement that the caller of the FIR filter must supply data on every clock cycle, as
we are no longer checking the
FirPtr->InputValid bit.
The final change to produce the single cycle FIR filter is to remove the accumulator and send instead
write the result of the call to the
RecurseAdd macro expression directly to the output register of the
filter, as shown below:
FirPtr->Output = RecurseAdd(MultResults, Taps-1);
As for the input, this imposes the requirement that the caller of the FIR filter must read data from the
output on every clock cycle.
The
FirWrite and FirRead macros and the interface structure must be updated accordingly, as there
is no longer any need for registers to check the validity of the input and output data. The modified
versions are shown below:
www.celoxica.com
Page 112