User manual

Tutorial: Using the logic estimator
Now rebuild the project for EDIF, and open Summary.html in the folder
PDK/Tutorials/General/TutorialFIR/Version1/EDIF. The summary file shows logic area and delay estimation for
the project, as shown below. As we improve the FIR in the next stages of the tutorial, you can refer back
to the summary on this page to compare the area and delay of new versions.
LOGIC ESTIMATION SUMMARY FOR VERSION1 PROJECT
The next stage in the tutorial is to improve the performance of the FIR by reducing the number of cycles
it takes to produce each output.
9.3 Using parallel multipliers
The previous version of the FIR (Initial version (see page 101)) took a large number of clock cycles to
generate each output, as it had to loop through all the filter taps performing MAC operations. In this
version we will use a bank of parallel multipliers so that the products of the data samples and coefficients
can all be calculated in a single cycle, and we will also add all these products in a single cycle. The
changes are in the
Version2 project in the TutorialFIR workspace, accessible from
Start>Programs>Celoxica>Platform Developer's Kit>Tutorials>TutorialFIR on the Start Menu.
To perform all the multiplications in one cycles we use the following code:
signed ResultWidth MultResults[Taps];
par (i = 0; i < Taps; i++)
{
MultResults[i] = FirPtr->Coeffs[i] * adjs(DataArray[i], ResultWidth);
}
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