User manual

Tutorial: Using the logic estimator
par
{
FirPtr->Output = Accumulator;
FirPtr->OutputValid = 1;
}
The main function in
fir1.hcc is set up to read input data from a file using chanin during simulation,
and to read from an interface when built for EDIF. Build the project for
Debug, and start the simulation.
The input data will be read from the file
input.txt, and the filtered output will be written to the file output.txt.
You will need to stop the simulation manually, as the filter is designed to run continuously.
Change the Active Configuration to
EDIF as shown below:
SELECTING EDIF FROM CONFIGURATION DROP-DOWN LIST.
Open the Project Settings dialog from the Project->Settings menu. Select the Chip tab and ensure that a
specific
Family and Device have been selected, as shown below:
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