Specifications

Installation and set-up
4.9 Ethernet
The RC200/203 is fitted with a Standard Microsystems Corporation LAN91C111 Ethernet device. It
supports 8-bit and 16-bit access to the FPGA. The device has a clock input of 25MHz, generated from
the CPLD. For more information about the device refer to the
RC200 data sheets (see page 34).
Ethernet pins Function RC200 FPGA pins (in
ascending order)
RC203 FPGA pins (in
ascending order)
ED0 - ED15 Data [15:0]
M21, N22, N21, P22, P21,
R21, T22, T21, U22, U21,
V21, W22, W21, Y22, Y21,
M17
P23, R24, R23, T24, T23,
U23, V24, V23, W24, W23,
Y23, AA24, AA23, AB24,
AB23, P19
EC0 - EC2 Address [2:0] M18, M20, M19 P20, P22, P21
EC3 and EC4 Not byte enable N20, N19 R22, R21
EC5 Not Read P20 T22
EC6 Not Write P19 T21
EC7 Interrupt R20 U22
EC8
Asynchronous ready
pin (Ardy)
R19 U21
EC9 Reset T20 V22
4.10 Video input processor
The RC200/203 board is fitted with a Philips SAA7113H Video Input Processor, enabling the FPGA to
capture S Video, CVBS and Camera input.
The FPGA can decode RGB to:
• NTSC or PAL using the AD725 RGB to NTSC/PAL encoder
• VGA output using the ADV7123 RGB to VGA encoder
Video input control and data pins
The video input has 8 data pins and 6 control lines:
Video input pins Function RC200 FPGA Pins (in
ascending order)
RC203 FPGA Pins (in
ascending order)
VIND0 – VIND7 Data pins [7:0]
AA20, AA18, AA17, AB17,
AA16, AB16, AA15, AA14
AC22, AC20, AC19, AD19,
AC18, AD18, AC17, AC16
VINC0 RTS1 W20 AA22
VINC1 RTS0 N17 R19
VINC2 RTCO P17 T19
VINC3 SCL N18 R20
VINC4 SDA P18 T20
VINC5 CEP R18 U20
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