Specifications

Installation and set-up
Pins connecting RAM Bank 0 to the FPGA
SSRAM pin Function Rc200 FPGA pins (in
ascending order)
RC203 FPGA pins (in
ascending order)
S0D0 -
S0D35
Data [35:0]
K20, L19, L20, K18, L18,
E18, F18, G18, H18, J18,
J17, K17, B12, A13, B13,
A14, B14, B15, A16, B16,
A17, B17, B18, A19, B19,
C12, D12, C13, D13, C14,
D14, C15, D15, C16, D16,
C17
M22, N21, N22, M20, N20,
G20, H20, J20, K20, L20,
L19, M19, D14, C15, D15,
C16, D16, D17, C18, D18,
C19, D19, D20, C21, D21,
E14, F14, E15, F15, E16,
F16, E17, F17, E18, F18,
E19
S0A0 -
S0A19
Address [19:0]
C21, C22, D21, D22, E21,
F21, F22, G21, G22, H21,
J21, J22, K21, K22, L22, L21,
E19, E20, F19, F20
E23, E24, F23, F24, G23,
H23, H24, J23, J24, K23,
L23, L24, M23, M24, N24,
N23, G21, G22, H21, H22
S0C0 CLK F12 H14
S0C1 nCS2 (not Chip Select) G19 J21
S0C2 R/nW (Read not Write) G20 J22
S0C4 - S0C7 Not Byte Enable pins J20, K19, H20, J19 L22, M21, K22, L21
Pins connecting RAM Bank 1 to the FPGA
SSRAM pin Function RC200 FPGA pins (in
ascending order)
RC203 FPGA pins (in
ascending order)
S1D0 -
S1D35
Data [35:0]
D7, C7, D8, C8, D9, C9, D10,
C10, E11, F11, E4, E5, E6,
E7, E8, E9, E10, F9, F10, C2,
C1, D2, D1, E2, F2, F1, G2,
G1, H2, J2, J1, K2, K1, L2,
E3, F4
F9, E9, F10, E10, F11, E11,
F12, E12, G13, H13, G6,
G7, G8, G9, G10, G11, G12,
H11, H12, E4, E3, F4, F3,
G4, H4, H3, J4, J3, K4, L4,
L3, M4, M3, N4, G5, H6
S1A0 -
S1A19
Address [19:0]
D17, C18, D18, F13, F14,
E13, E14, E15, E16, E17, B4,
A4, B5, B6, A6, B7, A7, B8,
B9, A9
F19, E20, F20, H15, H16,
G15, G16, G17, G18, G19,
D6, C6, D7, D8, C8, D9, C9,
D10, D11, C11
S1C0 CLK D11 F13
S1C1 nCS2 (not Chip Select) B10 D112
S1C2 R/nW (Read not Write) A10 C12
S1C4 - S1C7 Not Byte Enable pins D6, C6, C4, C5 F8, E8, E6, E7
4.8 Clock generator (PLL)
The RC200/203 board has a Cypress CY22393 Programmable Clock Generator. The generator is
programmed to provide the following clocks:
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