Specifications

Installation and set-up

Address value Description

Bit 0: SmartMedia nCS signal

Bit 1: SmartMedia CLE signal

Bit 2: SmartMedia ALE signal

Bit 3: Disable SmartMedia state machine

Bit 4: Master FPGA nPROG pin (inverted by CPLD)

Bit 5: Not used (Write 0)

Bit 6: PLL clock pin (I

C bus)

Bit 7: PLL data pin (I

C bus 1 = Tristate (input) 0=0)

4 Not used

5 Not used

6 Not used

7 CPLD version ID (0x51)

4.4 FPGA

The RC200 board has a Xilinx Virtex-II FPGA (part: XC2V1000-4FG456C on RC200 and

XC2V3000-4FG676 on RC203). The device has direct connections to the following devices:

• CPLD

• ZBT RAM

• Ethernet

• Clock generator

• Video input

• Video DAC

• RGB to PAL/NTSC encoder

• Audio codec

• RS-232

• PS/2 connectors

• Expansion header

• 2 seven-segment displays

• 2 blue LEDs

• 2 contact switches

• Bluetooth (if fitted)

• TFT Flat screen (if fitted)

• Touchscreen (if fitted)

Details of pin connections are given in the sections about these devices.

rd using Handel-C, remember that the pins should be listed If you are programming the boa

in reverse (descending) order.

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