Specifications

Installation and set-up
CPLD pins Signal Parallel port pins
76 ParSCTL 13
77 ParPE 12
78 Parnwait 11
79 ParINIT 10
80 Pardata7 9
81 Pardata6 8
82 Pardata5 7
85 Pardata4 6
86 Pardata3 5
89 Paraddr 17
90 Pardata2 4
91 Parnreset 16
92 Pardata1 3
93 Parnerror 15
94 Pardata0 2
95 Parndata 14
96 Parnwrite 1
The CPLD has 3 address pins. When the CPLD is communicating with the parallel port data lines, the 8
values within the 3-bit CPLD address are used as follows:
Address value Description
0 Read and write (i.e. data pins) when FPGA is in parallel port control mode
1 Read and write from host for SmartMedia
2 Not used
3 Read status of signals (8-bit data line from CPLD):
Bit 0: Master FPGA DONE signal
Bit 1: (not used; undefined)
Bit 2: FPGA nINIT signal
Bit 3: SmartMedia nBUSY signal
Bit 4: SmartMedia Detect (1 = SmartMedia inserted)
Bit 5: SmartMedia not Write Protect
Bit 6: SmartMedia state machine disable status
Bit 7: PLL data line (I
2
C bus)
Write status of signals:
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