Specifications

Installation and set-up
CPLD control
line
RC200
FPGA
pin
RC203
FPGA
pin
Function (normal FPGA
operation)
Function (parallel port
control mode)
P0 Y19 AB21 CCLK Not used
P1 AA3 AC5
PnCS (Parallel Not Chip
Select) - Input
nWR (Not Write) - Input
P2 Y4 AB6
nRDWR (Not Read Write) –
Input/Output
nRDWR (Not Read Write) -
Output
P3 A2 C4 nPROG Not used
P4 AB20 AD22 DONE Not used
P5 AA19 AC21 Address [0] – Output nINIT – Output
P6 AB19 AD21 Address [1] – Output nWAIT – Output
P7 R22 U24 Address [2] – Output nADDR – Input
P8 V22 Y24
nCS (Not Chip Select) –
Output
nDATA – Output
P9 T18 V20 Set high Set low
CPLD data line RC200 FPGA pin RC203 FPGA pin
FD0 V18 Y20
FD1 V17 VY19
FD2 W18 AA20
FD3 Y18 YAB20
FD4 Y5 AB7
FD5 W5 AA7
FD6 AB4 AD6
FD7 AA4 AC6
4.3.2 CPLD clock
The RC200 CPLD has a clock input of 50MHz from a 50MHz crystal oscillator module. This is divided by
2 to give an internal clock speed of 25MHz.
4.3.3 Register map in the CPLD for the FPGA
The RC200 CPLD has 3 address lines:
CPLD pins RC200 FPGA pins RC203 FPGA pins
P5 Addr[0] AA19 AC21
P6 Addr[1] AB19 AD21
P7 Addr[2] R22 U24
Only the lower 5 of the 8 possible values within the 3-bit CPLD address are used by the FPGA:
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