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Platform Developer’s Kit

RC200/203 Manual

Summary of content (76 pages)

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Platform Developer’s Kit RC200/203 Manual
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RC200/203 Manual Celoxica, the Celoxica logo and Handel-C are trademarks of Celoxica Limited. All other products or services mentioned herein may be trademarks of their respective owners. Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder. The product described in this document is subject to continuous development and improvement.
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RC200/203 Manual Contents 1 RC200/203 BOARD .................................................................................................... 8 2 RC200/203 OVERVIEW................................................................................................ 9 2.1 STANDARD KIT ...................................................................................................... 9 2.2 PROFESSIONAL KIT ............................................................................................. 10 2.
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RC200/203 Manual 4.20 JTAG CONNECTOR ........................................................................................... 33 4.21 CAMERA AND CAMERA SOCKET .......................................................................... 33 4.22 BLUETOOTH MODULE ........................................................................................ 34 4.23 TOUCH SCREEN ................................................................................................ 34 4.24 DATA SHEETS AND SPECIFICATIONS....
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RC200/203 Manual 5.12.1 Video input management tasks ........................................................................................... 51 5.12.2 Selecting the video input ..................................................................................................... 51 5.12.3 Selecting the colour-encoding standard.............................................................................. 51 5.12.4 Reading a pair of YCrCb pixels ............................................................
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RC200/203 Manual Conventions The following conventions are used in this document. 2 Warning Message. These messages warn you that actions may damage your hardware. Ï Handy Note. These messages draw your attention to crucial pieces of information. Hexadecimal numbers will appear throughout this document. The convention used is that of prefixing the number with '0x' in common with standard C syntax.
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RC200/203 Manual Assumptions & Omissions This manual assumes that you: • have used Handel-C or have the Handel-C Language Reference Manual • are familiar with common programming terms (e.g. functions) • are familiar with your operating system (Linux or MS Windows) This manual does not include: • instruction in VHDL or Verilog • instruction in the use of place and route tools • tutorial example programs. These are provided in the Handel-C User Manual Page 7 www.celoxica.
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RC200/203 board 1 RC200/203 board The RC200 and RC203 are platforms for evaluation and development of high-performance FPGA-based applications. The platforms include a Xilinx Virtex-II FPGA, external memory, programmable clocks, Ethernet, Audio, Video, SmartMedia, Parallel port, RS-232 and PS/2 keyboard and mouse. Supporting software includes PAL, DSM, the RC200 PSL, and the FTU2 File Transfer Utility.
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RC200/203 board 2 RC200/203 overview The devices and connectors on the board are shown in the overview of devices (see page 13) and overview of connectors (see page 14). Note: the Xilinx Virtex II device on the RC203 has part number XC2V3000-FG676. 2.
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RC200/203 board • • Microphone in • Line in (Stereo) • Line/Headphone out (Stereo) Connector for SmartMedia Flash memory for storage of BIT files • CPLD for configuration/reconfiguration and SmartMedia management • • Power-on load from SmartMedia • Load when SmartMedia installed • Reconfigure on demand from FPGA Parallel port connector and cable, for BIT-file download and host communication with FPGA • RS-232 • PS/2 keyboard and mouse connectors • 2 seven-segment displays • 2 blue LEDs • 2 m
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RC200/203 board 2.4 RC200/203 support software The following software support for the RC200/203 is provided as part of the Platform Developer's Kit: • RC200 Platform Support Library (PSL) • RC200 Platform Abstraction Layer (PAL) implementation • Data Stream Manager (DSM) implementation for MicroBlaze soft-core microprocessor • FTU2 program (for Windows NT4, Windows 2000 and Windows XP). Allows you you to download BIT files onto the FPGA. Page 11 www.celoxica.
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RC200/203 overview 3 Installation and set-up Unpacking the board You should take care to avoid static discharge when handling the RC200/203 board, as this may damage it. You are recommended to use an earth strap. If an earth strap is not available, ensure that you make contact with earth before and during handling of the board, and only handle the board by its edges. Connecting the cables The board must be powered down before you attach cables.
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Installation and set-up 4 Hardware description This section describes the devices on the RC200, how to program the FPGA and how to transfer data between the host, SmartMedia and FPGA. Schematics for the board are available in InstallDir\PDK\Documentation\PSL\RC200\RC200VBDOC.pdf for the RC200 or in InstallDir\PDK\Documentation\PSL\RC203\RC203VBDOC.pdf for the RC203 (for installations using PDK3.1 or later).
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Installation and set-up 4.2 RC200/203 connectors CONNECTORS ON THE RC200/203 4.3 CPLD The RC200/203 has a Xilinx XC95144XL 3.3V CPLD. The CPLD is connected to the: • FPGA • Parallel port • SmartMedia Flash RAM • JTAG chain The CPLD can configure the FPGA with data received from SmartMedia memory, or via the parallel port. 4.3.1 Control and data pins The RC200 CPLD has 10 control lines and 8 data lines. 3 of the control lines are used as an address bus.
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Installation and set-up CPLD control line RC200 FPGA pin RC203 FPGA pin Function (normal FPGA operation) Function (parallel port control mode) P0 Y19 AB21 CCLK Not used P1 AA3 AC5 PnCS (Parallel Not Chip Select) - Input nWR (Not Write) - Input P2 Y4 AB6 nRDWR (Not Read Write) – Input/Output nRDWR (Not Read Write) Output P3 A2 C4 nPROG Not used P4 AB20 AD22 DONE Not used P5 AA19 AC21 Address [0] – Output nINIT – Output P6 AB19 AD21 Address [1] – Output nWAIT – Output
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Installation and set-up 0 Control of SmartMedia and PLL Bit 0: SmartMedia nCS signal Bit 1: SmartMedia CLE signal Bit 2: SmartMedia ALE signal Bit 3: Disable SmartMedia state machine Bit 4: Not used (Write 0) Bit 5: Not used (Write 0) Bit 6: PLL clock pin (I2C bus) Bit 7: PLL data pin (I2C bus 1 = Tristate (input) 0=0) 1 Read status Register Bit 0: Master FPGA DONE signal Bit 1: (not used; undefined) Bit 2: FPGA nINIT signal Bit 3: SmartMedia nBUSY signal Bit 4: SmartMedia Detect (1 = SmartMedia inserte
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Installation and set-up CPLD pins Signal Parallel port pins 76 ParSCTL 13 77 ParPE 12 78 Parnwait 11 79 ParINIT 10 80 Pardata7 9 81 Pardata6 8 82 Pardata5 7 85 Pardata4 6 86 Pardata3 5 89 Paraddr 17 90 Pardata2 4 91 Parnreset 16 92 Pardata1 3 93 Parnerror 15 94 Pardata0 2 95 Parndata 14 96 Parnwrite 1 The CPLD has 3 address pins.
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Installation and set-up Address value Description Bit 0: SmartMedia nCS signal Bit 1: SmartMedia CLE signal Bit 2: SmartMedia ALE signal Bit 3: Disable SmartMedia state machine Bit 4: Master FPGA nPROG pin (inverted by CPLD) Bit 5: Not used (Write 0) Bit 6: PLL clock pin (I2C bus) Bit 7: PLL data pin (I2C bus 1 = Tristate (input) 0=0) 4 Not used 5 Not used 6 Not used 7 CPLD version ID (0x51) 4.
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Installation and set-up The FPGA also has access to the parallel port and to the SmartMedia Flash memory through the CPLD. You can program the FPGA via the CPLD from the SmartMedia Flash memory, or from the parallel port. 4.4.
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Installation and set-up 4.4.4 Programming the FPGA from SmartMedia You can program the RC200 Virtex-II from BIT files loaded onto the SmartMedia device. The BIT files can be in exactly the same format as if you were programming from the parallel port. There is no need to change or remove the header.
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Installation and set-up 4.4.7 Writing data to the CPLD from the FPGA To write from the RC200 FPGA to the CPLD: 1. Set up the address and data bus if not already tristated. 2. Wait at least 10ns. 3. Set nCS low. 4. Wait at least 10ns. 5. Set nRDWR high and enable the data bus. 6. Wait at least 40ns. 7. Tristate nRDWR. 8. Set nCS high. 9. Tristate the data bus. 4.4.8 Transferring data between the FPGA and host The parallel port can read and write data to the RC200 FPGA by accessing CPLD address 0.
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Installation and set-up 4.6 SmartMedia Flash memory The RC200/203 has a socket for a SmartMedia Flash memory device (connector CN7 at the top left of the board). The Professional and Expert versions of the RC200/203 are provided with a 16-MB SmartMedia card. You can use any SmartMedia device between 4 and 128 megabytes. Ï The RC200/203 Platform Support Library abstracts away some of the intricacies of the physical layer control mechanism within the SmartMedia driver.
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Installation and set-up 4. Deassert ALE (CPLD address 0, bit 2). 5. Assert CLE (CPLD address 0, bit 1). 6. Write a command to address 2. 7. Deassert CLE. 8. Read or write to SmartMedia using address 2. 4.6.3 Parallel port access of SmartMedia The RC200 SmartMedia is accessed from the parallel port via the CPLD. A typical sequence of events for programming the SmartMedia from the parallel port might be: 1. Check the SmartMedia device is fitted (address 3, bit 4). 2.
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Installation and set-up Pins connecting RAM Bank 0 to the FPGA SSRAM pin Function Rc200 FPGA pins (in ascending order) RC203 FPGA pins (in ascending order) S0D0 S0D35 Data [35:0] K20, L19, L20, K18, L18, E18, F18, G18, H18, J18, J17, K17, B12, A13, B13, A14, B14, B15, A16, B16, A17, B17, B18, A19, B19, C12, D12, C13, D13, C14, D14, C15, D15, C16, D16, C17 M22, N21, N22, M20, N20, G20, H20, J20, K20, L20, L19, M19, D14, C15, D15, C16, D16, D17, C18, D18, C19, D19, D20, C21, D21, E14, F14, E15, F15, E
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Installation and set-up Clock generator pin Description RC200 FPGA pin RC203 FPGA pin GCLK2P GCLK5P CLKUSER. Clock used to feed the FPGA. Y12 AB14 24.576MHz clock. Used to feed video input and audio chip. B11 D13 GCLK6S 25.175MHz clock. Used to feed VGA output (640 x 480 at 60Hz). C11 E13 GCLK0P 27MHz video input clock. AB12 AD14 GCLK1P 50MHz crystal clock. This is used to feed the CPLD.
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Installation and set-up 4.9 Ethernet The RC200/203 is fitted with a Standard Microsystems Corporation LAN91C111 Ethernet device. It supports 8-bit and 16-bit access to the FPGA. The device has a clock input of 25MHz, generated from the CPLD. For more information about the device refer to the RC200 data sheets (see page 34).
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Installation and set-up 4.11 Video output processors The RC200/203 can convert digital RGB input into outputs for a VGA screen, a TV (PAL or NTSC) or an LCD screen. OVERVIEW OF VIDEO OUTPUT PROCESSING 4.11.1 Digital / Analogue converter The Analog Devices ADV7123 High speed video DAC can convert 30-bit digital input to VGA output or RGB input for the NTSC/PAL encoder. For more information on this device, please refer to the RC200 data sheets (see page 34).
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Installation and set-up 4.11.2 RGB to NTSC/PAL encoder The RC200/203 has an Analog Devices AD725 RGB to NTSC/PAL Encoder. This receives RGB input from the video DAC. For more information on this device, please refer the RC200 data sheets (see page 34). NTSC/PAL encoder pins Function RC200 FPGA pins RC203 FPGA pins TV0 Standard pin AB14 AD16 TV1 Hsync pin AA13 AC15 TV2 Vsync pin AB13 AD15 4.11.
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Installation and set-up Description Function Rc200 FPGA pins RC203 FPGA pins Serial0 CTS (Clear To Send) T19 V21 Serial1 RxD (Receive data) U20 W22 Serial2 RTS (Request To Send) U19 W21 Serial3 TxD (Transmit data) V20 Y22 4.14 Mouse and keyboard PS/2 ports The RC200/203 board has two PS/2 ports, labelled Mouse and Keyboard on the PCB. These are 6-pin mini DIN sockets that will accept any standard PS/2 mouse or keyboard.
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Installation and set-up 7-segment pins Display segment RC200 FPGA pins RC203FPGA pins A1 a G3 J5 B1 b H4 K6 C1 c L3 N5 D1 d L4 N6 E1 e K3 M5 F1 f F3 H5 G1 g G4 J6 DP1 decimal place L5 N7 Display 1 (display on right-hand side) 7-segment pins Display segment RC200 FPGA pins RC203FPGA pins A2 a J4 L6 B2 b J3 L5 C2 c H5 K7 D2 d F5 H7 E2 e L6 N8 F2 f H3 K5 G2 g G5 J7 DP2 decimal place K4 M6 4.
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Installation and set-up Expansion header pins ATA function Expansion header function RC200 RC203 FPGA pins FPGA pins 1 Reset IO0 R2 U4 2 GND GND - - 3 D7 IO2 M2 P4 4 D8 IO1 M1 P3 5 D6 IO4 N2 R4 6 D9 IO3 N1 R3 7 D5 IO6 P2 T4 8 D10 IO5 P1 T3 9 D4 IO8 M4 P6 10 D11 IO7 M3 P5 11 D2 IO10 N4 R6 12 D12 IO9 N3 R5 13 D2 IO12 P3 T5 14 D13 IO11 P4 T6 15 D1 IO14 R4 U6 16 D14 IO13 R3 U5 17 D0 IO16 T3 V5 18 D15 IO15 T2 V4 19
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Installation and set-up Expansion header pins ATA function Expansion header function RC200 RC203 FPGA pins FPGA pins 41 Pin removed Pin removed - - 42 Pin removed Pin removed - - 43 IO32 IO32 V1 Y3 44 +3.3v +3.3v (0.5Amps max) - - 45 IO33 IO33 N5 R7 46 +5v +5v (0.5Amps max) - - 47 CLK0 CLK0 AA11 AC13 48 +12v +12v (0.5Amps max) - - 49 CLK1 CLK1 W11 AA13 50 GND GND - - 4.
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Installation and set-up 4.19 Reset button The reset button on the RC200/203 is next to the power input. It clears the FPGA program, and reboots the FPGA from SmartMedia, if a SmartMedia card is present. 4.20 JTAG connector The JTAG connector on the RC200/203 is next to the reset button. JTAG connector pinout is as follows: Pin JTAG Function 1 TMS 2 - 3 TDI 4 TDO 5 - 6 TCK 7 VCC (+3.3V) 8 GND 9 VCC (+3.3V) Some of the RC200/203 devices are connected into a JTAG chain.
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Installation and set-up 4.22 Bluetooth module A Mitsumi WML-C09 Bluetooth module is provided on the RC200/203 Expert board. It is connected directly to the FPGA. Bluetooth pins Function RC200 FPGA pins RC203 FPGA pins BT0 RX pin W13 AA15 BT1 TX pin Y13 AB15 BT2 RTS pin W12 AA14 BT3 CTS pin V12 Y14 BT4 Reset pin U12 W14 4.23 Touch screen A Fujitsu Components N010-0554-T042 6.4 inch touch screen is provided as an optional feature with the RC200/203 Expert board.
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Installation and set-up Device Information Xilinx XC95144XL CPLD Click on the XC9500XL link at: http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp then choose the XC95144XL PDF Xilinx Virtex-II FPGA part: XC2V1000-4FG456C IEEE 1284 Parallel Port specification Click on the Virtex-II link at: http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp http://www.fapo.com/ieee1284.htm SmartMedia http://www.ssfdc.or.jp/english/ IDT IDT71T75702 ZBT RAM http://www.idt.com/docs/71T75702_DS_59004.
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Hardware description 5 RC200/203 PSL reference The RC200/203 Platform Support Library is provided as part of the Platform Developer's Kit. Throughout this documentation "RC200" should be taken to refer to both RC200 and RC203 unless explicitly noted otherwise. This Library targets both RC200 and RC203 boards although there are four slightly different versions: • rc200.hcl targets the Standard and Professional versions of the RC200 • rc200e.hcl targets the Expert version of the RC200. • rc203.
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Hardware description 5.2.1 Specifying a clock source # define RC200_CLOCK_USER # define RC200_CLOCK_EXPCLK0 # define RC200_CLOCK_EXPCLK1 Description To use CLKUSER (the FPGA clock) or one of the expansion header clocks, define one of the macros above before you include rc200.hch in your source code. The specified clock will be used by any subsequent void main (void) definition. Defining RC200_CLOCK_USER will select the CLKUSER source from the clock generator.
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Hardware description Description Returns a compile-time constant Boolean to indicate whether the board is an "Expert" model featuring expanded RAM, Bluetooth, LCD and touch screen. You can use this to determine which board your code should be compiled for. For example, you could use an if...select statement to choose code specific to Expert boards. 5.4 LED macros The LED macros target the blue LEDs on the RC200. The green LEDs on the RC200 are controlled by the CPLD and cannot be programmed.
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Hardware description 5.5 Push button macros To test whether the buttons on or off, you can either use RC200ButtonRead() and set Index to 0 to test Button0 or to 1 to test Button1, or you can use one of the RC200Button*Read() macros to target a specific button. If you want to control both buttons at once, use RC200ButtonReadMask(). 5.5.1 RC200ButtonRead() extern macro expr RC200ButtonRead (Index); Parameters: Index: Button index, of type unsigned 1.
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Hardware description Parameters: Shape: Bitmask control value, of type unsigned 8. Timing: 1 clock cycle. Description: Sets a particular shape in the seven-segment display. Shape is a binary mask where 1 means ON and 0 means OFF. Each of the eight bits corresponds to a segment of the display (7-segments for the digit and one for the decimal point). The segments are numbered as shown below. The right-most bit in Shape targets segment a, and the left-most bit targets the decimal point (dp).
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Hardware description If you only want to write part of a word of data, you can mask the address using one of the RC200PL1RAM*SetWriteAddressMask() macros. 5.7.1 RAM management tasks extern macro proc RC200PL1RAM0Run (ClockRate); extern macro proc RC200PL1RAM1Run (ClockRate); Parameters: ClockRate: Clock rate of the clock domain of the call to this macro, in Hz. Timing: Does not terminate in normal use. Description: Runs the device management tasks for RAM.
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Hardware description 5.7.4 Reading from RAM extern macro proc RC200PL1RAM0Read (DataPtr); extern macro proc RC200PL1RAM1Read (DataPtr); Parameters: DataPtr: Pointer to an lvalue of type unsigned 36. Timing: 1 clock cycle. Description: Reads a single item of data from the address specified by the call to the RC200PL1RAM*SetReadAddress() on the previous cycle. 5.7.
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Hardware description Parameters: DataPtr: Pointer to an lvalue of type unsigned 8. Timing: 1 or more clock cycles (the read is blocked until data is ready). Description: Reads a single item of data from the mouse PS/2 port and stores it in the lvalue pointed at by DataPtr. Note that these are raw bytes from the mouse. To do interpreted access (e.g. mouse positions) you should use the PAL PS/2 API. 5.8.
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Hardware description Parameters: Data: data value of type unsigned 8. Timing: 1 or more clock cycles (until data is sent). Description: Writes a single item of data to the keyboard PS/2 port from the expression Data. Note that these are raw bytes from the keyboard. To do interpreted access (e.g. ASCII keyboard characters) you should use the PAL PS/2 API. 5.9 RS-232 port macros To read from or write to the RS-232 port, you need to: 1. Call RC200RS232Run().
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Hardware description Baud code Baud selected (number of transitions per second) RC200RS232_75Baud 75 RC200RS232_110Baud 100 RC200RS232_300Baud 300 RC200RS232_1200Baud 1200 RC200RS232_2400Baud 2400 RC200RS232_9600Baud 9600 RC200RS232_19200Baud 19200 RC200RS232_38400Baud 38400 RC200RS232_57600Baud 57600 RC200RS232_115200Baud 115200 RC200RS232_230400Baud 230400 RC200RS232_460800Baud 460800 RC200RS232_921600Baud 921600 Selecting the parity extern macro proc RC200RS232SetParity (Pari
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Hardware description 5.9.2 Reading from the RS-232 port extern macro proc RC200RS232Read (DataPtr); Parameters: DataPtr: Pointer to an lvalue of type unsigned 8. Timing: 1 or more clock cycles (the read is blocked until data is ready). Description: Reads a single item of data from the RS232 port and stores it in the lvalue pointed at by DataPtr. 5.9.3 Writing to the RS-232 port extern macro proc RC200RS232Write (Data); Parameters: Data: data value of type unsigned 8.
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Hardware description Parameters: XPtr: Pointer to an lvalue of type unsigned 12. YPtr: Pointer to an lvalue of type unsigned 12. TouchPtr: Pointer to an lvalue of type unsigned 1. Timing: 1 clock cycle. Description: Returns the last sensed position of the pointing device on the touch screen, in raw coordinates. The coordinates range from 0 to 4095 and are independent of display resolution.
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Hardware description Parameters: Mode: Video mode expression, see below. ClockRate: Clock rate of the clock domain of the call to this macro, in Hz. Timing: Does not terminate in normal use. Description: Drives the video output in the selected mode. You must run this macro in parallel with accesses to the device. Mode must be one of the expressions listed below. The VGA modes drive the VGA connector with VESA GTF compatible timings. The horizontal resolution will adapt according to ClockRate.
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Hardware description Parameters: None. Timing: Typically 1 clock cycle. Description: Enables the video output. You need to call this macro before you call RC200VideoOutWrite24() or RC200VideoOutWrite30(). 5.11.
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Hardware description 5.11.5 Writing a pixel extern macro proc RC200VideoOutWrite24 (RGB24); extern macro proc RC200VideoOutWrite30 (RGB30); Parameters: RGB24: Compound colour expression, of type unsigned 24. RGB30: Compound colour expression, of type unsigned 30. Timing: 1 clock cycle. Description: Writes a single pixel to the display, at the current scan position. In both cases the video output expression is a concatenation of the red, green and blue components (i.e. R @ G @ B).
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Hardware description 5.12 Video input macros There are 3 different macros for reading data: • RC200VideoInReadPixelPairYCrCb() reads a pair of YCrCb pixels. YCrCb is the native output from the video decoder, and so this macro requires less hardware than the other two read macros. • RC200VideoInReadPixelPairRGB() reads a pair of RGB pixels. • RC200VideoInReadPixelRGB() reads a single RGB pixel. Before you use one of these macros you need to: 1.
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Hardware description Parameters: Standard: A code selecting the TV colour-encoding standard. Possible values RC200VideoInStandardPALNTSC or RC200VideoInStandardSECAM The first code selects PAL or NTSC and the second selects SECAM. The default value is RC200VideoInStandardPALNTSC. Timing: 1 or more clock cycles. Description: Selects which colour-encoding standard to expect at the selected input. You need to call RC200VideoInSetInput() before using this macro.
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Hardware description Parameters: XPtr: Pointer to an lvalue of type unsigned 9. YPtr: Pointer to an lvalue of type unsigned 9. LeftRGBPtr: Pointer to an lvalue of type unsigned 24. RightRGBPtr: Pointer to an lvalue of type unsigned 24. Timing: 1 or more clock cycles (read blocks until data is ready) Description: Reads a pair of RGB encoded pixels from the video input selected by RC200VideoInSetInput(). This form of input requires a colour space converter which is built automatically.
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Hardware description 5.13 Audio I/O macros To use the audio macros you need to: 1. Call RC200AudioRun() in parallel with the rest of your audio code. 2. Set the audio input to the line in connector or the microphone using RC200AudioInSetInput(). 5.13.1 Audio codec management tasks extern macro proc RC200AudioRun (ClockRate); Parameters: ClockRate: Clock rate of the clock domain of the call to this macro, in Hz. Timing: Does not terminate in normal use.
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Hardware description Parameters: Mute: Data value of type unsigned 1. LeftVol: Data value of type unsigned 4. RightVol: Data value of type unsigned 4. Timing: 1 or more clock cycles. Description: LeftVol and RightVol set the gain level (amount of increase) of the ADC input amplifiers, from 0dB to +22.5dB in 1.5dB steps. Mute is a Boolean where "1" = muted. 5.13.
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Hardware description Parameters: Mute: Data value of type unsigned 1. LeftVol: Data value of type unsigned 5. RightVol: Data value of type unsigned 5. Timing: 1 or more clock cycles. Description: LeftVol and RightVol set the gain level of the DAC output amplifiers, from 0dB to -46.5dB in -1.5dB steps. Mute is a boolean where "1" = muted. 5.13.8 Setting the output sample rate extern macro proc RC200AudioOutSetSampleRate (SampleRateCode); Parameters: SampleRateCode: a code selecting the sampling rate.
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Hardware description 5.14.1 Bluetooth management tasks extern macro proc RC200BluetoothRun (ClockRate); Parameters: ClockRate: Clock rate of the clock domain of the call to this macro, in Hz. Timing: Does not terminate in normal use. Runs the device management tasks for the Bluetooth interface. You must run this macro in parallel with accesses to the device. Description: 5.14.2 Resetting the Bluetooth device extern macro proc RC200BluetoothReset (); Parameters: None. Timing: 1 or more clock cycles.
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Hardware description as this preserves the CIS block and misses out bad blocks. For devices of less than 16 megabytes, you can only use physical addressing. 5.15.1 Using the SmartMedia macros Accessing the SmartMedia card To use the RC200 PSL macros to access SmartMedia, you need to: 1. Call the RC200SmartMediaRun() macro in parallel with the other SmartMedia macros and in parallel to RC200CPLDRun(). 2. Enable the CPLD using RC200CPLDEnable(). 3.
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Hardware description 2 Do not use the SmartMedia macros at the same time as any other accesses to the CPLD. If you have called RC200SmartMediaSetLogicalAddress(), RC200SmartMediaSetAddress(), RC200SmartMediaRead() or RC200SmartMediaWrite(), you need to get the return value from RC200SmartMediaOperationEnd() before accessing the CPLD again. If you have used any of the other SmartMedia macros, you can access the CPLD after they have completed. 5.15.
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Hardware description 5.15.5 Resetting the SmartMedia extern macro proc RC200SmartMediaReset (ResultPtr); Parameters: ResultPtr: Pointer to register of type unsigned 1. Returns 0 for success, 1 for failure. Timing: 110 clock cycles or more. Description: Resets the SmartMedia device. You can reset the device at any time; the reset operation is the only one that can be run ignoring the busy status returned by the SmartMedia device. 5.15.
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Hardware description You can only use logical addressing on cards of 16 megabytes or more. To use logical addressing, you need to format the card using the command-line version of the Celoxica FTU2 program. The logical formatting operation creates a logical address map on the third valid block in the card. This is to allow for corrupt blocks near the start of the card; the CIS/IDI fields are on the first valid block.
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Hardware description Parameters: ResultPtr: Pointer to register of type unsigned 1. Returns 0 for success, 1 for failure. Timing: 250 clock cycles or more. Description: This macro checks to see if the SmartMedia card is formatted according to the SmartMedia Physical Specification. If the card is unformatted, it formats it. ResultPtr indicates whether the card has been successfully formatted or not. ResultPtr also returns 0 if the card was already formatted. 5.15.
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Hardware description Parameters: DataPtr: Register to store the data to be read, of type unsigned 8. LastData: Compile time constant to indicate the end of the data. Set LastData to 1 to indicate that the last byte of data is being read. Timing: 160 clock cycles or more (including setting the address). Description: Reads sequential data, one byte at a time, from the SmartMedia device. You need to call RC200SmartMediaSetAddress() before you call this macro for the first time.
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Hardware description Parameters: ResultPtr: Pointer to register of type unsigned 1. Returns 0 for success, 1 for failure. Timing: 1 or more clock cycles. It will take more than one clock cycle if you call the macro directly after the last call to RC200SmartMediaRead() or RC200SmartMediaWrite(). Description: You can only call this macro after a call to RC200SmartMediaRead() or RC200SmartMediaWrite().
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Hardware description Parameters: ClockRate: Clock rate of the clock domain of the call to this macro, in Hz. MACAddress: Ethernet MAC address to be used by the Ethernet chip, of type unsigned 48. Timing: Does not terminate in normal use. Description: Runs the device management tasks for the Ethernet interface. You must run this macro in parallel with accesses to the device. 5.16.
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Hardware description Parameters: None. Timing: Dependant on clock rate. Minimum: 4 clock cycles. Description: Sets the reset pin low for at least 100ns, forcing the Ethernet chip to reset. You need to call RC200EthernetEnable() after you reset the device. 5.16.6 Reading a packet Starting the read process extern macro proc RC200EthernetReadBegin (StatusPtr, DestinationPtr, SourcePtr, DataByteCountPtr, ResultPtr); Parameters: StatusPtr: Pointer to data of type unsigned 16.
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Hardware description Completing the read process extern macro proc RC200EthernetReadEnd (ResultPtr); Parameters: ResultPtr: Pointer to data of type unsigned 1. Returns 1 (failure) or 0 (success). Timing: 7 clock cycles to 5ms, depending on the speed of response of the Ethernet device. Description: Completes the process of reading a packet from the Ethernet device. You must call this macro after all the data has been read from a packet. 5.16.
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Hardware description Parameters: Data: Data of type unsigned 8, containing a byte of data to write to the packet. ResultPtr: Pointer to data of type unsigned 1. Returns 1 (failure) or 0 (success). Timing: 1 or 6 clock cycles alternately. This is because the macro writes a byte at a time, but Ethernet accesses are 16-bit. When a byte of data is already buffered on the chip the write only takes 1 clock cycle. Timing may differ if other accesses to the chip precede a write operation.
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Hardware description 5.18 CPLD control You need to run the CPLD and enable it if you want to use: • the SmartMedia macros (see page 57) • the reconfiguration macro (see page 68) • the Send Protocol macros (see page 69) RC200CPLDRun() needs to be called in parallel to these macros, and RC200CPLDEnable() needs to be called before you access them. 5.18.
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Hardware description 1. Call RC200CPLDRun() and RC200CPLDEnable(). 2. Call RC200SendProtocolEnable() to enable the Send Protocol driver. 3. Call RC200SendProtocolWrite() or RC200SendProtocolRead(). 2 Do not use the Send Protocol macros at the same time as the SmartMedia macros. 5.19.1 Enabling the Send Protocol driver extern macro proc RC200SendProtocolEnable(); Parameters: None. Timing: 1 clock cycle. Description: Enables the Send Protocol driver.
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Hardware description Parameters: DataPtr: Pointer to data of type unsigned 8, to return data read from the host PC. Timing: Variable. Depends on whether host PC has sent data to read. Description: Reads one byte of data from the host PC and writes it to the FPGA. This macro will block if the host has not sent any data to be read. You must call RC200SendProtocolEnable() before using this macro. 5.
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RC200/203 PSL reference 6 Index expansion port pins.................................30, 73 A F audio ....................................................... 28, 55 FPGA ......................................................70, 72 Expert RC200 ...............................................
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RC200/203 PSL reference RC200....................................................... 8, 36 RC200EthernetReadEnd ..............................68 board version 37 RC200EthernetRun ......................................66 clock definitions 36 RC200EthernetWrite.....................................69 clock rate 37 RC200EthernetWriteBegin ...........................69 connectors 14 RC200EthernetWriteEnd ..............................70 data sheets 34 RC200ExpansionPins..........................
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RC200/203 PSL reference RC200SmartMediaSetAddress .............. 62, 63 PnCS signal 14 RC200SmartMediaWrite............................... 64 SmartMedia Detect signal 16 RC200TouchScreenReadRaw ..................... 46 SmartMedia...................................................22 RC200TouchScreenReadScaled ................. 47 address structure RC200TouchScreenRun .............................. 46 checking for errors 63, 65 RC200VideoInReadPixelPairYCrCb ............
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RC200/203 PSL reference TFT 28 writing data 50 Page 76 www.celoxica.