Specifications

Si100x Port mappings
ProcessorPortPin SNAPpyIO

ProcessorPortPin SNAPpyIO
P0.0ADC0V
REF
 0P2.1ADC17 10
P0.2ADC2RTS0 1P2.2ADC18 11
P0.3ADC3CTS0 2P2.3ADC19 12
P0.4ADC4TXD0 3P2.4ADC20 13
P0.5ADC5RXD0 4P2.5ADC21 14
P0.6ADC6CNVSTR 5P2.6ADC22 15
P1.5ADC13SPI_SPLK 6P2.7C2D 16
P1.6ADC14SPI_MISO 7 GPIO_0 17
P1.7ADC15SPI_MOSI 8 ANT_A 18
11
P2.0ADC16 9



“Wakeup” Pins
On an Si100x Wireless Module, any of the following IOs can be used to wake the processor:
IO0 Map to P0.0
IO1–IO5: Map to P0.2–P0.6
IO6–IO8: Map to P1.5–P1.7
Analog Input Pins
On the Si100x Wireless Module, 16 pins can be used as ADC inputs. P0.0-P0.6 (excepting P0.1) are
available as ADC0-ADC6 (excepting ADC1), P1.5-P1.7 as ADC13-15, and P2.0-P2.6 as ADC16-22,
are all available.
Serial port 0
Four IO pins can optionally function as UART0. IO4 becomes RXD0 and IO3 becomes TXD0. If
hardware flow control is required, IO2 becomes CTS0 and IO1 becomes RTS0.
PWM Output Pins
On the Si100x Wireless Module, you can configure up to six PWM pins. These are user-assignable to
any available IO (except IO16-IO18).
SPI
Three IO pins can optionally function as an SPI bus. IO6 becomes SCLK, IO7 becomes MISO, and
IO8 becomes MOSI.
11
IO18 is available for output only.
Page 166 of 202 SNAP Reference Manual Document Number 600-0007K