Specifications

ATMEL ATmega128RFA1
In addition to modules built on the SNAP Engine footprint, you will find SNAP running on ATMEL
chips. See the following section for details unique to the SNAP Engine form factor.
IO pins
The ATmega128RFA1 supports 38 IO pins. Any of the 38 IO can be a digital input, or digital output.
Wakeup pins
Seventeen of the 38 IO support a hardware “wakeup” capability. See IO 0-7, 8-11, 16, and 20-23.
Setting the unit to wake from an edge-triggered interrupt on INT4-INT7 (SNAPpy IOs 20-23) will
work, but will result in higher power consumption during sleep. If you must have an edge-triggered
wake signal, it is recommended you use a different pin.
Analog inputs
Eight of the 38 IO can be used as analog inputs. See IO 24-31.
UART0
Four pins support UART 0, see IO 16, 17, 20, and 21. If you do not need RTS/CTS signals, then IO 20
and 21 are available for other usage.
UART1
Four pins support UART 1, see IO 10, 11, 12, and 23. If you do not need RTS/CTS signals, then IO 12
and 23 are available for other usage.
SPI
Three pins can optionally be used for SPI. See IO 28-30.
NOTE – these are not the hardware SPI pins. SNAPpy SPI is done via software emulation.
You will also need one “SPI Chip Select” pin per external SPI device. Any available IO pin can be
used for this purpose.
I
2
C
Two pins can optionally be used for I
2
C, see IO 24 and 25.
NOTE – these are not the hardware I
2
C pins. SNAPpy I
2
C is done via software emulation.
PWM
Eight pins can optionally be used as Pulse Width Modulation (PWM) outputs, see IO 4-7, 19-21, and
37.
The table on the following page summarizes the IO mapping on the ATmega128RFA1 chip.
You will notice that the “IO” numbering scheme chosen simply steps through the available ports in
alphabetical order: ports B, D, E, F, and G. (There is no port A or port C on an ATmega128RFA1).
SNAP Reference Manual Document Number 600-0007K Page 153 of 202