Specifications

Timers
Normally the MC1321x uses timer 2 in the hardware for its system clock. Feature bit 0x40 of NV
Parameter 11 can be set to instruct SNAP to use timer 1 instead. This affects the availability of PWM
on associated pins. Refer to the Freescale documentation for details on how to make use of this.
MC1321x IO Mapping
ProcessorPortPin SNAPpyIOProcessorPortPin SNAPpyIO
PTA0/KBD0 0PTC1/RxD2 17
PTA1/KBD1 1 PTC2 18
PTA2/KBD2 2 PTC3 19
PTA3/KBD3 3 PTC4 20
PTA4/KBD4 4 PTC5 21
PTA5/KBD5 5 PTC6 22
PTA6/KBD6 6 PTC7 23
PTA7/KBD7 7PTD2/TPM1CH2 24
PTB0/AD0 8PTD4/TPM2CH1 25
PTB1/AD1 9

PTD5/TPM2CH2 26
PTB2/AD2 10

PTD6/TPM2CH3 27
PTB3/AD3 11

PTD7/TPM2CH4 28
PTB4/AD4 12

PTE0/TxD1 29
PTB5/AD5 13

PTE1/RxD1 30
PTB6/AD6 14

PTG1/XTAL 31
PTB7/AD7 15

PTG2/EXTAL 32
PTC0/TxD2 16
 
NOTE – in the above table we are using the chip manufacturer’s naming scheme. Because of this, the
first UART is designated with a 1 and the second UART is designated with a 2. Within SNAPpy, we
refer to these as UARTs 0 and 1.
Page 128 of 202 SNAP Reference Manual Document Number 600-0007K