User Manual

Physical Layer DSP Hardware Engine
Dedicated logic is used for forward error correction, header error control, cyclic
redundancy check, encryption, data whitening, access code correlation and audio
transcoding to translate between A-law, µ-law and linear voice data from the host and
A-law, µ-law and Continuously Variable Slope Delta (CVSD) voice data over the air,
voice interpolation for lost packets and rate mismatches are performed by the
software.
Burst Mode Controller
During radio transmission the Burst Mode Controller (BMC) constructs a packet from
header information previously loaded into memory-mapped registers by the software
and payload data/voice taken from the appropriate ring buffer in RAM. During radio
receptions, the burst mode controller stores the packet header in memory-mapped
registers and the payload data in the appropriate ring buffer in RAM. This architecture
minimises the intervention required by the processor during transmission and
reception.
Micro-controller, Interrupt Controller and Event Timer
The micro-controller, interrupt controller and event timer run the Bluetooth software
stack and control the radio and host interfaces. A 16-bit RISC micro-controller is used
for low power consumption and efficient use of memory.
Memory Management Unit
The memory management unit provides a number of dynamically allocated ring
buffers that hold the data which is in transit between the host and the air or vice versa.
The dynamic allocation of memory ensures efficient use of the available RAM and is
performed by a hardware memory management unit to minimise the overheads on the
processor during data/voice transfers.
RAM
32Kbytes of on-chip RAM is provided and is shared between the ring buffers used to
hold voice/data for each active connection and the general purpose memory required
by the Bluetooth stack.
ROM
Up to 8Mbits of external Flash or masked programmed ROM (16 bit data words) can
be attached giving maximum flexibility for running complete applications on chip. The
ROM can be programmed over the synchronous serial/UART or USB interfaces after
the device is mounted in the target application.