Specifications

— 13 —
Pin No. Signal I/O Function
64,65 OSC I/O I/O Clock terminal (DT-26S)
67,69~71 V1 ~ 4 Voltage for LCD driver
OFF: 0[V] ON: V1: 0.64(Light) ~ 1.29(Dark)[V]
V2: 1.29 ~ 2.56 [V]
V3: 3.99 ~ 2.71 [V]
V4: 4.64 ~ 3.99 [V]
68 NC - Not used
72 INTO In Low battery detection INTO<5.2[V]=> No power on
73 STNT - GND/0[V]
74 VLCD In Power supply/5.3[V]
75 ~ 171 S0 ~ 95 Out Segment signal for display
172 ~ 199 C5 ~ 32 Out Common signal for display
168, 200 NC - Not used
6-2. RAM: MB84256A-70/10LL (LSI 3)
A0 ~ A16 : Address input signal
IO0 ~ IO7 : Data signal (Input/Output)
OE_ : Output enable signal
CE_ : Chip enable signal
A0 ~ A14 : Address input signal
IO0 ~ IO7 : Data signal (Input/Output)
WE : Write enable signal
CS : Chip select signal
OE : Output enable signal
ROM: µPD23C1001EAGW-K81 (LSI 4)
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
IO0
IO1
IO2
GND
VCC
WE
A13
A8
A9
A11
OE
A10
CS
IO7
IO6
IO5
IO4
IO3
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
A13
A8
A9
A11
A10
IO7
IO6
IO5
IO4
IO3
IO0
IO1
IO2
VSS
CPU (CSRA2)
DATA BUS
ADDRESS BUS
DATA BUS
ADDRESS BUS
MB84256A-70/10LL
CPU (WEB)
0.1µ
VPP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
IO0
IO1
IO2
GND
VCC
PGM
NC
A14
A13
A8
A9
A11
OE_
A10
CE_
IO7
IO6
IO5
IO4
IO3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
16
13
14
15
RA16
RA15
A12
A7
A6
A5
A4
A3
A2
A1
A0
A14
A13
A8
A9
A11
A10
IO7
IO6
IO5
IO4
IO3
IO0
IO1
IO2
VSS
CPU (CSROM)
DATA BUS
ADDRESS BUS
DATA BUS
ADDRESS BUS
µPD23C1001EAGW-K81